65cea4708e
Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.
Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.
Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.
Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
82 lines
3.8 KiB
Python
82 lines
3.8 KiB
Python
# Copyright (c) 2013-2014 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Vasileios Spiliopoulos
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# Akash Bagdia
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# Stephan Diestelhorst
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from m5.params import *
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from m5.SimObject import SimObject
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from m5.proxy import *
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# Abstract clock domain
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class ClockDomain(SimObject):
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type = 'ClockDomain'
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cxx_header = "sim/clock_domain.hh"
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abstract = True
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# Source clock domain with an actual clock, and a list of voltage and frequency
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# op points
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class SrcClockDomain(ClockDomain):
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type = 'SrcClockDomain'
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cxx_header = "sim/clock_domain.hh"
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# Single clock frequency value, or list of frequencies for DVFS
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# Frequencies must be ordered in descending order
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# Note: Matching voltages should be defined in the voltage domain
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clock = VectorParam.Clock("Clock period")
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# A source clock must be associated with a voltage domain
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voltage_domain = Param.VoltageDomain("Voltage domain")
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# Domain ID is an identifier for the DVFS domain as understood by the
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# necessary control logic (either software or hardware). For example, in
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# case of software control via cpufreq framework the IDs should correspond
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# to the neccessary identifier in the device tree blob which is interpretted
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# by the device driver to communicate to the domain controller in hardware.
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domain_id = Param.Int32(-1, "domain id")
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# Initial performance level from the list of available operation points
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# Defaults to maximum performance
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init_perf_level = Param.UInt32(0, "Initial performance level")
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# Derived clock domain with a parent clock domain and a frequency
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# divider
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class DerivedClockDomain(ClockDomain):
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type = 'DerivedClockDomain'
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cxx_header = "sim/clock_domain.hh"
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clk_domain = Param.ClockDomain("Parent clock domain")
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clk_divider = Param.Unsigned(1, "Frequency divider")
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