gem5/src/mem/simple_mem.cc
Brandon Potter a928a438b8 style: [patch 3/22] reduce include dependencies in some headers
Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.
2016-11-09 14:27:40 -06:00

298 lines
8.8 KiB
C++

/*
* Copyright (c) 2010-2013, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ron Dreslinski
* Ali Saidi
* Andreas Hansson
*/
#include "mem/simple_mem.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/Drain.hh"
using namespace std;
SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
AbstractMemory(p),
port(name() + ".port", *this), latency(p->latency),
latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
retryReq(false), retryResp(false),
releaseEvent(this), dequeueEvent(this)
{
}
void
SimpleMemory::init()
{
AbstractMemory::init();
// allow unconnected memories as this is used in several ruby
// systems at the moment
if (port.isConnected()) {
port.sendRangeChange();
}
}
Tick
SimpleMemory::recvAtomic(PacketPtr pkt)
{
panic_if(pkt->cacheResponding(), "Should not see packets where cache "
"is responding");
access(pkt);
return getLatency();
}
void
SimpleMemory::recvFunctional(PacketPtr pkt)
{
pkt->pushLabel(name());
functionalAccess(pkt);
bool done = false;
auto p = packetQueue.begin();
// potentially update the packets in our packet queue as well
while (!done && p != packetQueue.end()) {
done = pkt->checkFunctional(p->pkt);
++p;
}
pkt->popLabel();
}
bool
SimpleMemory::recvTimingReq(PacketPtr pkt)
{
panic_if(pkt->cacheResponding(), "Should not see packets where cache "
"is responding");
panic_if(!(pkt->isRead() || pkt->isWrite()),
"Should only see read and writes at memory controller, "
"saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
// we should not get a new request after committing to retry the
// current one, but unfortunately the CPU violates this rule, so
// simply ignore it for now
if (retryReq)
return false;
// if we are busy with a read or write, remember that we have to
// retry
if (isBusy) {
retryReq = true;
return false;
}
// technically the packet only reaches us after the header delay,
// and since this is a memory controller we also need to
// deserialise the payload before performing any write operation
Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
pkt->headerDelay = pkt->payloadDelay = 0;
// update the release time according to the bandwidth limit, and
// do so with respect to the time it takes to finish this request
// rather than long term as it is the short term data rate that is
// limited for any real memory
// calculate an appropriate tick to release to not exceed
// the bandwidth limit
Tick duration = pkt->getSize() * bandwidth;
// only consider ourselves busy if there is any need to wait
// to avoid extra events being scheduled for (infinitely) fast
// memories
if (duration != 0) {
schedule(releaseEvent, curTick() + duration);
isBusy = true;
}
// go ahead and deal with the packet and put the response in the
// queue if there is one
bool needsResponse = pkt->needsResponse();
recvAtomic(pkt);
// turn packet around to go back to requester if response expected
if (needsResponse) {
// recvAtomic() should already have turned packet into
// atomic response
assert(pkt->isResponse());
Tick when_to_send = curTick() + receive_delay + getLatency();
// typically this should be added at the end, so start the
// insertion sort with the last element, also make sure not to
// re-order in front of some existing packet with the same
// address, the latter is important as this memory effectively
// hands out exclusive copies (shared is not asserted)
auto i = packetQueue.end();
--i;
while (i != packetQueue.begin() && when_to_send < i->tick &&
i->pkt->getAddr() != pkt->getAddr())
--i;
// emplace inserts the element before the position pointed to by
// the iterator, so advance it one step
packetQueue.emplace(++i, pkt, when_to_send);
if (!retryResp && !dequeueEvent.scheduled())
schedule(dequeueEvent, packetQueue.back().tick);
} else {
pendingDelete.reset(pkt);
}
return true;
}
void
SimpleMemory::release()
{
assert(isBusy);
isBusy = false;
if (retryReq) {
retryReq = false;
port.sendRetryReq();
}
}
void
SimpleMemory::dequeue()
{
assert(!packetQueue.empty());
DeferredPacket deferred_pkt = packetQueue.front();
retryResp = !port.sendTimingResp(deferred_pkt.pkt);
if (!retryResp) {
packetQueue.pop_front();
// if the queue is not empty, schedule the next dequeue event,
// otherwise signal that we are drained if we were asked to do so
if (!packetQueue.empty()) {
// if there were packets that got in-between then we
// already have an event scheduled, so use re-schedule
reschedule(dequeueEvent,
std::max(packetQueue.front().tick, curTick()), true);
} else if (drainState() == DrainState::Draining) {
DPRINTF(Drain, "Draining of SimpleMemory complete\n");
signalDrainDone();
}
}
}
Tick
SimpleMemory::getLatency() const
{
return latency +
(latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
}
void
SimpleMemory::recvRespRetry()
{
assert(retryResp);
dequeue();
}
BaseSlavePort &
SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
return MemObject::getSlavePort(if_name, idx);
} else {
return port;
}
}
DrainState
SimpleMemory::drain()
{
if (!packetQueue.empty()) {
DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
return DrainState::Draining;
} else {
return DrainState::Drained;
}
}
SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
SimpleMemory& _memory)
: SlavePort(_name, &_memory), memory(_memory)
{ }
AddrRangeList
SimpleMemory::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
ranges.push_back(memory.getAddrRange());
return ranges;
}
Tick
SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
{
return memory.recvAtomic(pkt);
}
void
SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
{
memory.recvFunctional(pkt);
}
bool
SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
{
return memory.recvTimingReq(pkt);
}
void
SimpleMemory::MemoryPort::recvRespRetry()
{
memory.recvRespRetry();
}
SimpleMemory*
SimpleMemoryParams::create()
{
return new SimpleMemory(this);
}