70798b1ba0
Fixing an issue with regStats not calling the parent class method for most SimObjects in Gem5. This causes issues if one adds new stats in the base class (since they are never initialized properly!). Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
586 lines
20 KiB
C++
586 lines
20 KiB
C++
/*
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* Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lisa Hsu
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*/
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#include "gpu-compute/tlb_coalescer.hh"
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#include <cstring>
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#include "debug/GPUTLB.hh"
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TLBCoalescer::TLBCoalescer(const Params *p) : MemObject(p),
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clock(p->clk_domain->clockPeriod()), TLBProbesPerCycle(p->probesPerCycle),
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coalescingWindow(p->coalescingWindow),
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disableCoalescing(p->disableCoalescing), probeTLBEvent(this),
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cleanupEvent(this)
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{
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// create the slave ports based on the number of connected ports
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for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
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cpuSidePort.push_back(new CpuSidePort(csprintf("%s-port%d", name(), i),
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this, i));
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}
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// create the master ports based on the number of connected ports
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for (size_t i = 0; i < p->port_master_connection_count; ++i) {
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memSidePort.push_back(new MemSidePort(csprintf("%s-port%d", name(), i),
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this, i));
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}
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}
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BaseSlavePort&
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TLBCoalescer::getSlavePort(const std::string &if_name, PortID idx)
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{
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if (if_name == "slave") {
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if (idx >= static_cast<PortID>(cpuSidePort.size())) {
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panic("TLBCoalescer::getSlavePort: unknown index %d\n", idx);
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}
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return *cpuSidePort[idx];
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} else {
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panic("TLBCoalescer::getSlavePort: unknown port %s\n", if_name);
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}
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}
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BaseMasterPort&
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TLBCoalescer::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "master") {
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if (idx >= static_cast<PortID>(memSidePort.size())) {
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panic("TLBCoalescer::getMasterPort: unknown index %d\n", idx);
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}
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return *memSidePort[idx];
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} else {
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panic("TLBCoalescer::getMasterPort: unknown port %s\n", if_name);
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}
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}
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/*
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* This method returns true if the <incoming_pkt>
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* can be coalesced with <coalesced_pkt> and false otherwise.
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* A given set of rules is checked.
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* The rules can potentially be modified based on the TLB level.
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*/
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bool
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TLBCoalescer::canCoalesce(PacketPtr incoming_pkt, PacketPtr coalesced_pkt)
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{
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if (disableCoalescing)
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return false;
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TheISA::GpuTLB::TranslationState *incoming_state =
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safe_cast<TheISA::GpuTLB::TranslationState*>(incoming_pkt->senderState);
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TheISA::GpuTLB::TranslationState *coalesced_state =
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safe_cast<TheISA::GpuTLB::TranslationState*>(coalesced_pkt->senderState);
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// Rule 1: Coalesce requests only if they
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// fall within the same virtual page
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Addr incoming_virt_page_addr = roundDown(incoming_pkt->req->getVaddr(),
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TheISA::PageBytes);
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Addr coalesced_virt_page_addr = roundDown(coalesced_pkt->req->getVaddr(),
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TheISA::PageBytes);
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if (incoming_virt_page_addr != coalesced_virt_page_addr)
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return false;
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//* Rule 2: Coalesce requests only if they
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// share a TLB Mode, i.e. they are both read
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// or write requests.
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BaseTLB::Mode incoming_mode = incoming_state->tlbMode;
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BaseTLB::Mode coalesced_mode = coalesced_state->tlbMode;
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if (incoming_mode != coalesced_mode)
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return false;
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// when we can coalesce a packet update the reqCnt
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// that is the number of packets represented by
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// this coalesced packet
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if (!incoming_state->prefetch)
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coalesced_state->reqCnt.back() += incoming_state->reqCnt.back();
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return true;
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}
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/*
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* We need to update the physical addresses of all the translation requests
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* that were coalesced into the one that just returned.
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*/
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void
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TLBCoalescer::updatePhysAddresses(PacketPtr pkt)
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{
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Addr virt_page_addr = roundDown(pkt->req->getVaddr(), TheISA::PageBytes);
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DPRINTF(GPUTLB, "Update phys. addr. for %d coalesced reqs for page %#x\n",
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issuedTranslationsTable[virt_page_addr].size(), virt_page_addr);
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TheISA::GpuTLB::TranslationState *sender_state =
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safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
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TheISA::GpuTlbEntry *tlb_entry = sender_state->tlbEntry;
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assert(tlb_entry);
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Addr first_entry_vaddr = tlb_entry->vaddr;
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Addr first_entry_paddr = tlb_entry->paddr;
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int page_size = tlb_entry->size();
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bool uncacheable = tlb_entry->uncacheable;
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int first_hit_level = sender_state->hitLevel;
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bool valid = tlb_entry->valid;
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// Get the physical page address of the translated request
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// Using the page_size specified in the TLBEntry allows us
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// to support different page sizes.
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Addr phys_page_paddr = pkt->req->getPaddr();
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phys_page_paddr &= ~(page_size - 1);
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for (int i = 0; i < issuedTranslationsTable[virt_page_addr].size(); ++i) {
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PacketPtr local_pkt = issuedTranslationsTable[virt_page_addr][i];
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TheISA::GpuTLB::TranslationState *sender_state =
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safe_cast<TheISA::GpuTLB::TranslationState*>(
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local_pkt->senderState);
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// we are sending the packet back, so pop the reqCnt associated
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// with this level in the TLB hiearchy
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if (!sender_state->prefetch)
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sender_state->reqCnt.pop_back();
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/*
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* Only the first packet from this coalesced request has been
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* translated. Grab the translated phys. page addr and update the
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* physical addresses of the remaining packets with the appropriate
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* page offsets.
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*/
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if (i) {
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Addr paddr = phys_page_paddr;
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paddr |= (local_pkt->req->getVaddr() & (page_size - 1));
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local_pkt->req->setPaddr(paddr);
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if (uncacheable)
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local_pkt->req->setFlags(Request::UNCACHEABLE);
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// update senderState->tlbEntry, so we can insert
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// the correct TLBEentry in the TLBs above.
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sender_state->tlbEntry =
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new TheISA::GpuTlbEntry(0, first_entry_vaddr, first_entry_paddr,
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valid);
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// update the hitLevel for all uncoalesced reqs
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// so that each packet knows where it hit
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// (used for statistics in the CUs)
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sender_state->hitLevel = first_hit_level;
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}
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SlavePort *return_port = sender_state->ports.back();
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sender_state->ports.pop_back();
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// Translation is done - Convert to a response pkt if necessary and
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// send the translation back
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if (local_pkt->isRequest()) {
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local_pkt->makeTimingResponse();
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}
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return_port->sendTimingResp(local_pkt);
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}
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// schedule clean up for end of this cycle
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// This is a maximum priority event and must be on
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// the same cycle as GPUTLB cleanup event to prevent
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// race conditions with an IssueProbeEvent caused by
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// MemSidePort::recvReqRetry
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cleanupQueue.push(virt_page_addr);
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if (!cleanupEvent.scheduled())
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schedule(cleanupEvent, curTick());
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}
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// Receive translation requests, create a coalesced request,
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// and send them to the TLB (TLBProbesPerCycle)
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bool
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TLBCoalescer::CpuSidePort::recvTimingReq(PacketPtr pkt)
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{
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// first packet of a coalesced request
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PacketPtr first_packet = nullptr;
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// true if we are able to do coalescing
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bool didCoalesce = false;
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// number of coalesced reqs for a given window
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int coalescedReq_cnt = 0;
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TheISA::GpuTLB::TranslationState *sender_state =
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safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
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// push back the port to remember the path back
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sender_state->ports.push_back(this);
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bool update_stats = !sender_state->prefetch;
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if (update_stats) {
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// if reqCnt is empty then this packet does not represent
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// multiple uncoalesced reqs(pkts) but just a single pkt.
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// If it does though then the reqCnt for each level in the
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// hierarchy accumulates the total number of reqs this packet
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// represents
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int req_cnt = 1;
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if (!sender_state->reqCnt.empty())
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req_cnt = sender_state->reqCnt.back();
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sender_state->reqCnt.push_back(req_cnt);
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// update statistics
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coalescer->uncoalescedAccesses++;
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req_cnt = sender_state->reqCnt.back();
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DPRINTF(GPUTLB, "receiving pkt w/ req_cnt %d\n", req_cnt);
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coalescer->queuingCycles -= (curTick() * req_cnt);
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coalescer->localqueuingCycles -= curTick();
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}
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// FIXME if you want to coalesce not based on the issueTime
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// of the packets (i.e., from the compute unit's perspective)
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// but based on when they reached this coalescer then
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// remove the following if statement and use curTick() or
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// coalescingWindow for the tick_index.
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if (!sender_state->issueTime)
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sender_state->issueTime = curTick();
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// The tick index is used as a key to the coalescerFIFO hashmap.
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// It is shared by all candidates that fall within the
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// given coalescingWindow.
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int64_t tick_index = sender_state->issueTime / coalescer->coalescingWindow;
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if (coalescer->coalescerFIFO.count(tick_index)) {
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coalescedReq_cnt = coalescer->coalescerFIFO[tick_index].size();
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}
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// see if we can coalesce the incoming pkt with another
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// coalesced request with the same tick_index
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for (int i = 0; i < coalescedReq_cnt; ++i) {
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first_packet = coalescer->coalescerFIFO[tick_index][i][0];
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if (coalescer->canCoalesce(pkt, first_packet)) {
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coalescer->coalescerFIFO[tick_index][i].push_back(pkt);
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DPRINTF(GPUTLB, "Coalesced req %i w/ tick_index %d has %d reqs\n",
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i, tick_index,
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coalescer->coalescerFIFO[tick_index][i].size());
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didCoalesce = true;
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break;
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}
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}
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// if this is the first request for this tick_index
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// or we did not manage to coalesce, update stats
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// and make necessary allocations.
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if (!coalescedReq_cnt || !didCoalesce) {
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if (update_stats)
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coalescer->coalescedAccesses++;
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std::vector<PacketPtr> new_array;
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new_array.push_back(pkt);
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coalescer->coalescerFIFO[tick_index].push_back(new_array);
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DPRINTF(GPUTLB, "coalescerFIFO[%d] now has %d coalesced reqs after "
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"push\n", tick_index,
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coalescer->coalescerFIFO[tick_index].size());
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}
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//schedule probeTLBEvent next cycle to send the
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//coalesced requests to the TLB
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if (!coalescer->probeTLBEvent.scheduled()) {
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coalescer->schedule(coalescer->probeTLBEvent,
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curTick() + coalescer->ticks(1));
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}
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return true;
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}
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void
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TLBCoalescer::CpuSidePort::recvReqRetry()
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{
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assert(false);
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}
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void
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TLBCoalescer::CpuSidePort::recvFunctional(PacketPtr pkt)
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{
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TheISA::GpuTLB::TranslationState *sender_state =
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safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
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bool update_stats = !sender_state->prefetch;
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if (update_stats)
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coalescer->uncoalescedAccesses++;
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// If there is a pending timing request for this virtual address
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// print a warning message. This is a temporary caveat of
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// the current simulator where atomic and timing requests can
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// coexist. FIXME remove this check/warning in the future.
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Addr virt_page_addr = roundDown(pkt->req->getVaddr(), TheISA::PageBytes);
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int map_count = coalescer->issuedTranslationsTable.count(virt_page_addr);
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if (map_count) {
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DPRINTF(GPUTLB, "Warning! Functional access to addr %#x sees timing "
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"req. pending\n", virt_page_addr);
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}
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coalescer->memSidePort[0]->sendFunctional(pkt);
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}
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AddrRangeList
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TLBCoalescer::CpuSidePort::getAddrRanges() const
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{
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// currently not checked by the master
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AddrRangeList ranges;
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return ranges;
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}
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bool
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TLBCoalescer::MemSidePort::recvTimingResp(PacketPtr pkt)
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{
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// a translation completed and returned
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coalescer->updatePhysAddresses(pkt);
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return true;
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}
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void
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TLBCoalescer::MemSidePort::recvReqRetry()
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{
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//we've receeived a retry. Schedule a probeTLBEvent
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if (!coalescer->probeTLBEvent.scheduled())
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coalescer->schedule(coalescer->probeTLBEvent,
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curTick() + coalescer->ticks(1));
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}
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void
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TLBCoalescer::MemSidePort::recvFunctional(PacketPtr pkt)
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{
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fatal("Memory side recvFunctional() not implemented in TLB coalescer.\n");
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}
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TLBCoalescer::IssueProbeEvent::IssueProbeEvent(TLBCoalescer * _coalescer)
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: Event(CPU_Tick_Pri), coalescer(_coalescer)
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{
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}
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const char*
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TLBCoalescer::IssueProbeEvent::description() const
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{
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return "Probe the TLB below";
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}
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/*
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* Here we scan the coalescer FIFO and issue the max
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* number of permitted probes to the TLB below. We
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* permit bypassing of coalesced requests for the same
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* tick_index.
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*
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* We do not access the next tick_index unless we've
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* drained the previous one. The coalesced requests
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* that are successfully sent are moved to the
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* issuedTranslationsTable table (the table which keeps
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* track of the outstanding reqs)
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*/
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void
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TLBCoalescer::IssueProbeEvent::process()
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{
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// number of TLB probes sent so far
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int sent_probes = 0;
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// rejected denotes a blocking event
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bool rejected = false;
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// It is set to true either when the recvTiming of the TLB below
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// returns false or when there is another outstanding request for the
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// same virt. page.
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DPRINTF(GPUTLB, "triggered TLBCoalescer IssueProbeEvent\n");
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for (auto iter = coalescer->coalescerFIFO.begin();
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iter != coalescer->coalescerFIFO.end() && !rejected; ) {
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int coalescedReq_cnt = iter->second.size();
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int i = 0;
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int vector_index = 0;
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DPRINTF(GPUTLB, "coalescedReq_cnt is %d for tick_index %d\n",
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coalescedReq_cnt, iter->first);
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while (i < coalescedReq_cnt) {
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++i;
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PacketPtr first_packet = iter->second[vector_index][0];
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// compute virtual page address for this request
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Addr virt_page_addr = roundDown(first_packet->req->getVaddr(),
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TheISA::PageBytes);
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// is there another outstanding request for the same page addr?
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int pending_reqs =
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coalescer->issuedTranslationsTable.count(virt_page_addr);
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if (pending_reqs) {
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DPRINTF(GPUTLB, "Cannot issue - There are pending reqs for "
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"page %#x\n", virt_page_addr);
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++vector_index;
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rejected = true;
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continue;
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}
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// send the coalesced request for virt_page_addr
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if (!coalescer->memSidePort[0]->sendTimingReq(first_packet)) {
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DPRINTF(GPUTLB, "Failed to send TLB request for page %#x",
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virt_page_addr);
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// No need for a retries queue since we are already buffering
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// the coalesced request in coalescerFIFO.
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rejected = true;
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++vector_index;
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} else {
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TheISA::GpuTLB::TranslationState *tmp_sender_state =
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safe_cast<TheISA::GpuTLB::TranslationState*>
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(first_packet->senderState);
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bool update_stats = !tmp_sender_state->prefetch;
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if (update_stats) {
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// req_cnt is total number of packets represented
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// by the one we just sent counting all the way from
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// the top of TLB hiearchy (i.e., from the CU)
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int req_cnt = tmp_sender_state->reqCnt.back();
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coalescer->queuingCycles += (curTick() * req_cnt);
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DPRINTF(GPUTLB, "%s sending pkt w/ req_cnt %d\n",
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coalescer->name(), req_cnt);
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// pkt_cnt is number of packets we coalesced into the one
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// we just sent but only at this coalescer level
|
|
int pkt_cnt = iter->second[vector_index].size();
|
|
coalescer->localqueuingCycles += (curTick() * pkt_cnt);
|
|
}
|
|
|
|
DPRINTF(GPUTLB, "Successfully sent TLB request for page %#x",
|
|
virt_page_addr);
|
|
|
|
//copy coalescedReq to issuedTranslationsTable
|
|
coalescer->issuedTranslationsTable[virt_page_addr]
|
|
= iter->second[vector_index];
|
|
|
|
//erase the entry of this coalesced req
|
|
iter->second.erase(iter->second.begin() + vector_index);
|
|
|
|
if (iter->second.empty())
|
|
assert(i == coalescedReq_cnt);
|
|
|
|
sent_probes++;
|
|
if (sent_probes == coalescer->TLBProbesPerCycle)
|
|
return;
|
|
}
|
|
}
|
|
|
|
//if there are no more coalesced reqs for this tick_index
|
|
//erase the hash_map with the first iterator
|
|
if (iter->second.empty()) {
|
|
coalescer->coalescerFIFO.erase(iter++);
|
|
} else {
|
|
++iter;
|
|
}
|
|
}
|
|
}
|
|
|
|
TLBCoalescer::CleanupEvent::CleanupEvent(TLBCoalescer* _coalescer)
|
|
: Event(Maximum_Pri), coalescer(_coalescer)
|
|
{
|
|
}
|
|
|
|
const char*
|
|
TLBCoalescer::CleanupEvent::description() const
|
|
{
|
|
return "Cleanup issuedTranslationsTable hashmap";
|
|
}
|
|
|
|
void
|
|
TLBCoalescer::CleanupEvent::process()
|
|
{
|
|
while (!coalescer->cleanupQueue.empty()) {
|
|
Addr cleanup_addr = coalescer->cleanupQueue.front();
|
|
coalescer->cleanupQueue.pop();
|
|
coalescer->issuedTranslationsTable.erase(cleanup_addr);
|
|
|
|
DPRINTF(GPUTLB, "Cleanup - Delete coalescer entry with key %#x\n",
|
|
cleanup_addr);
|
|
}
|
|
}
|
|
|
|
void
|
|
TLBCoalescer::regStats()
|
|
{
|
|
MemObject::regStats();
|
|
|
|
uncoalescedAccesses
|
|
.name(name() + ".uncoalesced_accesses")
|
|
.desc("Number of uncoalesced TLB accesses")
|
|
;
|
|
|
|
coalescedAccesses
|
|
.name(name() + ".coalesced_accesses")
|
|
.desc("Number of coalesced TLB accesses")
|
|
;
|
|
|
|
queuingCycles
|
|
.name(name() + ".queuing_cycles")
|
|
.desc("Number of cycles spent in queue")
|
|
;
|
|
|
|
localqueuingCycles
|
|
.name(name() + ".local_queuing_cycles")
|
|
.desc("Number of cycles spent in queue for all incoming reqs")
|
|
;
|
|
|
|
localLatency
|
|
.name(name() + ".local_latency")
|
|
.desc("Avg. latency over all incoming pkts")
|
|
;
|
|
|
|
localLatency = localqueuingCycles / uncoalescedAccesses;
|
|
}
|
|
|
|
|
|
TLBCoalescer*
|
|
TLBCoalescerParams::create()
|
|
{
|
|
return new TLBCoalescer(this);
|
|
}
|
|
|