152 lines
5.8 KiB
C++
152 lines
5.8 KiB
C++
/*
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* Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Sooraj Puthoor
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*/
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#include "gpu-compute/schedule_stage.hh"
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#include "gpu-compute/compute_unit.hh"
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#include "gpu-compute/gpu_static_inst.hh"
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#include "gpu-compute/vector_register_file.hh"
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#include "gpu-compute/wavefront.hh"
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ScheduleStage::ScheduleStage(const ComputeUnitParams *p)
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: numSIMDs(p->num_SIMDs),
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numMemUnits(p->num_global_mem_pipes + p->num_shared_mem_pipes)
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{
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for (int j = 0; j < numSIMDs + numMemUnits; ++j) {
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Scheduler newScheduler(p);
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scheduler.push_back(newScheduler);
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}
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}
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ScheduleStage::~ScheduleStage()
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{
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scheduler.clear();
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waveStatusList.clear();
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}
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void
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ScheduleStage::init(ComputeUnit *cu)
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{
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computeUnit = cu;
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_name = computeUnit->name() + ".ScheduleStage";
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for (int j = 0; j < numSIMDs + numMemUnits; ++j) {
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scheduler[j].bindList(&computeUnit->readyList[j]);
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}
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for (int j = 0; j < numSIMDs; ++j) {
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waveStatusList.push_back(&computeUnit->waveStatusList[j]);
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}
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dispatchList = &computeUnit->dispatchList;
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}
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void
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ScheduleStage::arbitrate()
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{
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// iterate over all Memory pipelines
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for (int j = numSIMDs; j < numSIMDs + numMemUnits; ++j) {
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if (dispatchList->at(j).first) {
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Wavefront *waveToMemPipe = dispatchList->at(j).first;
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// iterate over all execution pipelines
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for (int i = 0; i < numSIMDs + numMemUnits; ++i) {
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if ((i != j) && (dispatchList->at(i).first)) {
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Wavefront *waveToExePipe = dispatchList->at(i).first;
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// if the two selected wavefronts are mapped to the same
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// SIMD unit then they share the VRF
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if (waveToMemPipe->simdId == waveToExePipe->simdId) {
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int simdId = waveToMemPipe->simdId;
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// Read VRF port arbitration:
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// If there are read VRF port conflicts between the
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// a memory and another instruction we drop the other
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// instruction. We don't need to check for write VRF
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// port conflicts because the memory instruction either
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// does not need to write to the VRF (store) or will
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// write to the VRF when the data comes back (load) in
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// which case the arbiter of the memory pipes will
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// resolve any conflicts
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if (computeUnit->vrf[simdId]->
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isReadConflict(waveToMemPipe->wfSlotId,
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waveToExePipe->wfSlotId)) {
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// FIXME: The "second" member variable is never
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// used in the model. I am setting it to READY
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// simply to follow the protocol of setting it
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// when the WF has an instruction ready to issue
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waveStatusList[simdId]->at(waveToExePipe->wfSlotId)
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.second = READY;
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dispatchList->at(i).first = nullptr;
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dispatchList->at(i).second = EMPTY;
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break;
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}
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}
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}
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}
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}
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}
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}
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void
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ScheduleStage::exec()
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{
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for (int j = 0; j < numSIMDs + numMemUnits; ++j) {
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uint32_t readyListSize = computeUnit->readyList[j].size();
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// If no wave is ready to be scheduled on the execution resource
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// then skip scheduling for this execution resource
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if (!readyListSize) {
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continue;
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}
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Wavefront *waveToBeDispatched = scheduler[j].chooseWave();
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dispatchList->at(j).first = waveToBeDispatched;
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waveToBeDispatched->updateResources();
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dispatchList->at(j).second = FILLED;
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waveStatusList[waveToBeDispatched->simdId]->at(
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waveToBeDispatched->wfSlotId).second = BLOCKED;
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assert(computeUnit->readyList[j].size() == readyListSize - 1);
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}
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// arbitrate over all shared resources among instructions being issued
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// simultaneously
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arbitrate();
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}
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void
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ScheduleStage::regStats()
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{
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}
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