00a6346c91
we are removing doGmReturn from the GM pipe, and adding completeAcc() implementations for the HSAIL mem ops. the behavior in doGmReturn is dependent on HSAIL and HSAIL mem ops, however the completion phase of memory ops in machine ISA can be very different, even amongst individual machine ISA mem ops. so we remove this functionality from the pipeline and allow it to be implemented by the individual instructions.
103 lines
3.3 KiB
C++
103 lines
3.3 KiB
C++
/*
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* Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Sooraj Puthoor
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*/
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#ifndef __LOCAL_MEMORY_PIPELINE_HH__
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#define __LOCAL_MEMORY_PIPELINE_HH__
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#include <queue>
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#include <string>
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#include "gpu-compute/misc.hh"
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#include "params/ComputeUnit.hh"
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#include "sim/stats.hh"
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/*
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* @file local_memory_pipeline.hh
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*
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* The local memory pipeline issues newly created local memory packets
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* from pipeline to the LDS. This stage also retires previously issued
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* loads and stores that have returned from the LDS.
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*/
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class ComputeUnit;
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class Wavefront;
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class LocalMemPipeline
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{
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public:
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LocalMemPipeline(const ComputeUnitParams *params);
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void init(ComputeUnit *cu);
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void exec();
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std::queue<GPUDynInstPtr> &getLMReqFIFO() { return lmIssuedRequests; }
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std::queue<GPUDynInstPtr> &getLMRespFIFO() { return lmReturnedRequests; }
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bool
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isLMRespFIFOWrRdy() const
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{
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return lmReturnedRequests.size() < lmQueueSize;
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}
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bool
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isLMReqFIFOWrRdy(uint32_t pendReqs=0) const
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{
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return (lmIssuedRequests.size() + pendReqs) < lmQueueSize;
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}
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const std::string& name() const { return _name; }
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void regStats();
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void
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incLoadVRFBankConflictCycles(int num_cycles)
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{
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loadVrfBankConflictCycles += num_cycles;
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}
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private:
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ComputeUnit *computeUnit;
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std::string _name;
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int lmQueueSize;
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Stats::Scalar loadVrfBankConflictCycles;
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// Local Memory Request Fifo: all shared memory requests
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// are issued to this FIFO from the memory pipelines
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std::queue<GPUDynInstPtr> lmIssuedRequests;
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// Local Memory Response Fifo: all responses of shared memory
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// requests are sent to this FIFO from LDS
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std::queue<GPUDynInstPtr> lmReturnedRequests;
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};
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#endif // __LOCAL_MEMORY_PIPELINE_HH__
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