94d17a547c
The underlying assumption that all PPIs must be edge-triggered is strained when the architected timers and VGIC interfaces make level-behaviour observable. For example, a virtual timer interrupt 'goes away' when the hypervisor is entered and the vtimer is disabled; this requires a PPI to be de-activated. The new method simply clears the interrupt pending state.
96 lines
3.4 KiB
C++
96 lines
3.4 KiB
C++
/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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/** @file
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* Base class for ARM GIC implementations
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*/
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#ifndef __DEV_ARM_BASE_GIC_H__
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#define __DEV_ARM_BASE_GIC_H__
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#include "dev/io_device.hh"
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class Platform;
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class BaseGic : public PioDevice
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{
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public:
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typedef struct BaseGicParams Params;
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BaseGic(const Params *p);
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virtual ~BaseGic();
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const Params * params() const;
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/**
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* Post an interrupt from a device that is connected to the GIC.
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*
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* Depending on the configuration, the GIC will pass this interrupt
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* on through to a CPU.
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*
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* @param num number of interrupt to send
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*/
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virtual void sendInt(uint32_t num) = 0;
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/**
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* Interface call for private peripheral interrupts.
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*
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* @param num number of interrupt to send
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* @param cpu CPU to forward interrupt to
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*/
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virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
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virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
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/**
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* Clear an interrupt from a device that is connected to the GIC.
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*
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* Depending on the configuration, the GIC may de-assert it's CPU
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* line.
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*
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* @param num number of interrupt to send
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*/
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virtual void clearInt(uint32_t num) = 0;
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protected:
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/** Platform this GIC belongs to. */
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Platform *platform;
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};
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#endif
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