1fe5f63137
This change adds a Trace CPU param to exit simulation early, i.e. when the first (any one) trace execution is complete. With this change the user gets a choice to configure exit as either when the last CPU finishes (default) or first CPU finishes replay. Configuring an early exit enables simulating and measuring stats strictly when memory-system resources are being stressed by all Trace CPUs. Change-Id: I3998045fdcc5cd343e1ca92d18dd7f7ecdba8f1d Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
83 lines
3.7 KiB
Python
83 lines
3.7 KiB
Python
# Copyright (c) 2013 - 2016 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Radhika Jagtap
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# Andreas Hansson
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# Thomas Grass
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from m5.params import *
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from BaseCPU import BaseCPU
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class TraceCPU(BaseCPU):
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"""Trace CPU model which replays traces generated in a prior simulation
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using DerivO3CPU or its derived classes. It interfaces with L1 caches.
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"""
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type = 'TraceCPU'
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cxx_header = "cpu/trace/trace_cpu.hh"
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@classmethod
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def memory_mode(cls):
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return 'timing'
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@classmethod
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def require_caches(cls):
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return True
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def addPMU(self, pmu = None):
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pass
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@classmethod
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def support_take_over(cls):
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return True
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instTraceFile = Param.String("", "Instruction trace file")
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dataTraceFile = Param.String("", "Data dependency trace file")
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sizeStoreBuffer = Param.Unsigned(16, "Number of entries in the store "\
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"buffer")
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sizeLoadBuffer = Param.Unsigned(16, "Number of entries in the load buffer")
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sizeROB = Param.Unsigned(40, "Number of entries in the re-order buffer")
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# Frequency multiplier used to effectively scale the Trace CPU frequency
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# either up or down. Note that the Trace CPU's clock domain must also be
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# changed when frequency is scaled. A default value of 1.0 means the same
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# frequency as was used for generating the traces.
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freqMultiplier = Param.Float(1.0, "Multiplier scale the Trace CPU "\
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"frequency up or down")
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# Enable exiting when any one Trace CPU completes execution which is set to
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# false by default
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enableEarlyExit = Param.Bool(False, "Exit when any one Trace CPU "\
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"completes execution")
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