458d4a3c7b
The quiesce family of magic ops can be simplified by the inclusion of quiesceTick() and quiesce() functions on ThreadContext. This patch also gets rid of the FS guards, since suspending a CPU is also a valid operation for SE mode.
533 lines
17 KiB
C++
533 lines
17 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_THREAD_CONTEXT_HH__
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#define __CPU_THREAD_CONTEXT_HH__
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#include <iostream>
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#include <string>
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#include "arch/registers.hh"
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#include "arch/types.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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// @todo: Figure out a more architecture independent way to obtain the ITB and
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// DTB pointers.
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namespace TheISA
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{
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class Decoder;
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class TLB;
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}
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class BaseCPU;
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class CheckerCPU;
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class Checkpoint;
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class EndQuiesceEvent;
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class SETranslatingPortProxy;
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class FSTranslatingPortProxy;
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class PortProxy;
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class Process;
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class System;
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namespace TheISA {
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namespace Kernel {
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class Statistics;
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}
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}
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/**
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* ThreadContext is the external interface to all thread state for
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* anything outside of the CPU. It provides all accessor methods to
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* state that might be needed by external objects, ranging from
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* register values to things such as kernel stats. It is an abstract
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* base class; the CPU can create its own ThreadContext by either
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* deriving from it, or using the templated ProxyThreadContext.
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*
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* The ThreadContext is slightly different than the ExecContext. The
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* ThreadContext provides access to an individual thread's state; an
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* ExecContext provides ISA access to the CPU (meaning it is
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* implicitly multithreaded on SMT systems). Additionally the
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* ThreadState is an abstract class that exactly defines the
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* interface; the ExecContext is a more implicit interface that must
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* be implemented so that the ISA can access whatever state it needs.
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*/
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class ThreadContext
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::CCReg CCReg;
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typedef TheISA::MiscReg MiscReg;
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public:
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enum Status
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{
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/// Running. Instructions should be executed only when
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/// the context is in this state.
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Active,
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/// Temporarily inactive. Entered while waiting for
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/// synchronization, etc.
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Suspended,
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/// Permanently shut down. Entered when target executes
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/// m5exit pseudo-instruction. When all contexts enter
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/// this state, the simulation will terminate.
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Halted
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};
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virtual ~ThreadContext() { };
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virtual BaseCPU *getCpuPtr() = 0;
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virtual int cpuId() const = 0;
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virtual uint32_t socketId() const = 0;
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virtual int threadId() const = 0;
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virtual void setThreadId(int id) = 0;
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virtual int contextId() const = 0;
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virtual void setContextId(int id) = 0;
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virtual TheISA::TLB *getITBPtr() = 0;
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virtual TheISA::TLB *getDTBPtr() = 0;
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virtual CheckerCPU *getCheckerCpuPtr() = 0;
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virtual TheISA::Decoder *getDecoderPtr() = 0;
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virtual System *getSystemPtr() = 0;
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virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
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virtual PortProxy &getPhysProxy() = 0;
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virtual FSTranslatingPortProxy &getVirtProxy() = 0;
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/**
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* Initialise the physical and virtual port proxies and tie them to
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* the data port of the CPU.
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*
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* tc ThreadContext for the virtual-to-physical translation
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*/
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virtual void initMemProxies(ThreadContext *tc) = 0;
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virtual SETranslatingPortProxy &getMemProxy() = 0;
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virtual Process *getProcessPtr() = 0;
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virtual Status status() const = 0;
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virtual void setStatus(Status new_status) = 0;
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/// Set the status to Active.
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virtual void activate() = 0;
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/// Set the status to Suspended.
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virtual void suspend() = 0;
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/// Set the status to Halted.
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virtual void halt() = 0;
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/// Quiesce thread context
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void quiesce();
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/// Quiesce, suspend, and schedule activate at resume
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void quiesceTick(Tick resume);
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virtual void dumpFuncProfile() = 0;
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virtual void takeOverFrom(ThreadContext *old_context) = 0;
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virtual void regStats(const std::string &name) = 0;
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virtual EndQuiesceEvent *getQuiesceEvent() = 0;
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// Not necessarily the best location for these...
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// Having an extra function just to read these is obnoxious
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virtual Tick readLastActivate() = 0;
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virtual Tick readLastSuspend() = 0;
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virtual void profileClear() = 0;
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virtual void profileSample() = 0;
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virtual void copyArchRegs(ThreadContext *tc) = 0;
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virtual void clearArchRegs() = 0;
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//
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// New accessors for new decoder.
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//
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virtual uint64_t readIntReg(int reg_idx) = 0;
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virtual FloatReg readFloatReg(int reg_idx) = 0;
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virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
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virtual CCReg readCCReg(int reg_idx) = 0;
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virtual void setIntReg(int reg_idx, uint64_t val) = 0;
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virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
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virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
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virtual void setCCReg(int reg_idx, CCReg val) = 0;
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virtual TheISA::PCState pcState() = 0;
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virtual void pcState(const TheISA::PCState &val) = 0;
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virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
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virtual Addr instAddr() = 0;
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virtual Addr nextInstAddr() = 0;
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virtual MicroPC microPC() = 0;
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virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
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virtual MiscReg readMiscReg(int misc_reg) = 0;
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virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
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virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
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virtual int flattenIntIndex(int reg) = 0;
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virtual int flattenFloatIndex(int reg) = 0;
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virtual int flattenCCIndex(int reg) = 0;
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virtual int flattenMiscIndex(int reg) = 0;
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virtual uint64_t
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readRegOtherThread(int misc_reg, ThreadID tid)
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{
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return 0;
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}
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virtual void
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setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
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{
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}
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// Also not necessarily the best location for these two. Hopefully will go
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// away once we decide upon where st cond failures goes.
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virtual unsigned readStCondFailures() = 0;
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virtual void setStCondFailures(unsigned sc_failures) = 0;
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// Same with st cond failures.
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virtual Counter readFuncExeInst() = 0;
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virtual void syscall(int64_t callnum) = 0;
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// This function exits the thread context in the CPU and returns
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// 1 if the CPU has no more active threads (meaning it's OK to exit);
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// Used in syscall-emulation mode when a thread calls the exit syscall.
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virtual int exit() { return 1; };
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/** function to compare two thread contexts (for debugging) */
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static void compare(ThreadContext *one, ThreadContext *two);
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/** @{ */
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/**
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* Flat register interfaces
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*
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* Some architectures have different registers visible in
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* different modes. Such architectures "flatten" a register (see
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* flattenIntIndex() and flattenFloatIndex()) to map it into the
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* gem5 register file. This interface provides a flat interface to
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* the underlying register file, which allows for example
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* serialization code to access all registers.
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*/
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virtual uint64_t readIntRegFlat(int idx) = 0;
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virtual void setIntRegFlat(int idx, uint64_t val) = 0;
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virtual FloatReg readFloatRegFlat(int idx) = 0;
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virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
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virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
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virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
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virtual CCReg readCCRegFlat(int idx) = 0;
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virtual void setCCRegFlat(int idx, CCReg val) = 0;
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/** @} */
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};
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/**
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* ProxyThreadContext class that provides a way to implement a
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* ThreadContext without having to derive from it. ThreadContext is an
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* abstract class, so anything that derives from it and uses its
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* interface will pay the overhead of virtual function calls. This
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* class is created to enable a user-defined Thread object to be used
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* wherever ThreadContexts are used, without paying the overhead of
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* virtual function calls when it is used by itself. See
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* simple_thread.hh for an example of this.
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*/
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template <class TC>
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class ProxyThreadContext : public ThreadContext
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{
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public:
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ProxyThreadContext(TC *actual_tc)
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{ actualTC = actual_tc; }
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private:
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TC *actualTC;
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public:
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BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
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int cpuId() const { return actualTC->cpuId(); }
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uint32_t socketId() const { return actualTC->socketId(); }
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int threadId() const { return actualTC->threadId(); }
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void setThreadId(int id) { actualTC->setThreadId(id); }
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int contextId() const { return actualTC->contextId(); }
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void setContextId(int id) { actualTC->setContextId(id); }
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TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
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TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
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CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
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TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
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System *getSystemPtr() { return actualTC->getSystemPtr(); }
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TheISA::Kernel::Statistics *getKernelStats()
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{ return actualTC->getKernelStats(); }
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PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
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FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); }
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void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
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SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
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Process *getProcessPtr() { return actualTC->getProcessPtr(); }
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Status status() const { return actualTC->status(); }
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void setStatus(Status new_status) { actualTC->setStatus(new_status); }
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/// Set the status to Active.
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void activate() { actualTC->activate(); }
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/// Set the status to Suspended.
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void suspend() { actualTC->suspend(); }
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/// Set the status to Halted.
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void halt() { actualTC->halt(); }
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/// Quiesce thread context
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void quiesce() { actualTC->quiesce(); }
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/// Quiesce, suspend, and schedule activate at resume
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void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); }
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void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
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void takeOverFrom(ThreadContext *oldContext)
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{ actualTC->takeOverFrom(oldContext); }
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void regStats(const std::string &name) { actualTC->regStats(name); }
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EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
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Tick readLastActivate() { return actualTC->readLastActivate(); }
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Tick readLastSuspend() { return actualTC->readLastSuspend(); }
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void profileClear() { return actualTC->profileClear(); }
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void profileSample() { return actualTC->profileSample(); }
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// @todo: Do I need this?
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void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
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void clearArchRegs() { actualTC->clearArchRegs(); }
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx)
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{ return actualTC->readIntReg(reg_idx); }
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FloatReg readFloatReg(int reg_idx)
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{ return actualTC->readFloatReg(reg_idx); }
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FloatRegBits readFloatRegBits(int reg_idx)
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{ return actualTC->readFloatRegBits(reg_idx); }
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CCReg readCCReg(int reg_idx)
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{ return actualTC->readCCReg(reg_idx); }
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void setIntReg(int reg_idx, uint64_t val)
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{ actualTC->setIntReg(reg_idx, val); }
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void setFloatReg(int reg_idx, FloatReg val)
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{ actualTC->setFloatReg(reg_idx, val); }
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void setFloatRegBits(int reg_idx, FloatRegBits val)
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{ actualTC->setFloatRegBits(reg_idx, val); }
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void setCCReg(int reg_idx, CCReg val)
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{ actualTC->setCCReg(reg_idx, val); }
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TheISA::PCState pcState() { return actualTC->pcState(); }
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void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
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void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
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Addr instAddr() { return actualTC->instAddr(); }
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Addr nextInstAddr() { return actualTC->nextInstAddr(); }
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MicroPC microPC() { return actualTC->microPC(); }
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bool readPredicate() { return actualTC->readPredicate(); }
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void setPredicate(bool val)
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{ actualTC->setPredicate(val); }
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MiscReg readMiscRegNoEffect(int misc_reg) const
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{ return actualTC->readMiscRegNoEffect(misc_reg); }
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MiscReg readMiscReg(int misc_reg)
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{ return actualTC->readMiscReg(misc_reg); }
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{ return actualTC->setMiscRegNoEffect(misc_reg, val); }
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void setMiscReg(int misc_reg, const MiscReg &val)
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{ return actualTC->setMiscReg(misc_reg, val); }
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int flattenIntIndex(int reg)
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{ return actualTC->flattenIntIndex(reg); }
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int flattenFloatIndex(int reg)
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{ return actualTC->flattenFloatIndex(reg); }
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int flattenCCIndex(int reg)
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{ return actualTC->flattenCCIndex(reg); }
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int flattenMiscIndex(int reg)
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{ return actualTC->flattenMiscIndex(reg); }
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unsigned readStCondFailures()
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{ return actualTC->readStCondFailures(); }
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void setStCondFailures(unsigned sc_failures)
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{ actualTC->setStCondFailures(sc_failures); }
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void syscall(int64_t callnum)
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{ actualTC->syscall(callnum); }
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Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
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uint64_t readIntRegFlat(int idx)
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{ return actualTC->readIntRegFlat(idx); }
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void setIntRegFlat(int idx, uint64_t val)
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{ actualTC->setIntRegFlat(idx, val); }
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FloatReg readFloatRegFlat(int idx)
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{ return actualTC->readFloatRegFlat(idx); }
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void setFloatRegFlat(int idx, FloatReg val)
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{ actualTC->setFloatRegFlat(idx, val); }
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FloatRegBits readFloatRegBitsFlat(int idx)
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{ return actualTC->readFloatRegBitsFlat(idx); }
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void setFloatRegBitsFlat(int idx, FloatRegBits val)
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{ actualTC->setFloatRegBitsFlat(idx, val); }
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CCReg readCCRegFlat(int idx)
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{ return actualTC->readCCRegFlat(idx); }
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void setCCRegFlat(int idx, CCReg val)
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{ actualTC->setCCRegFlat(idx, val); }
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};
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/** @{ */
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/**
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* Thread context serialization helpers
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*
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* These helper functions provide a way to the data in a
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* ThreadContext. They are provided as separate helper function since
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* implementing them as members of the ThreadContext interface would
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* be confusing when the ThreadContext is exported via a proxy.
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*/
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void serialize(ThreadContext &tc, CheckpointOut &cp);
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void unserialize(ThreadContext &tc, CheckpointIn &cp);
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/** @} */
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/**
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* Copy state between thread contexts in preparation for CPU handover.
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*
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* @note This method modifies the old thread contexts as well as the
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* new thread context. The old thread context will have its quiesce
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* event descheduled if it is scheduled and its status set to halted.
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*
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* @param new_tc Destination ThreadContext.
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* @param old_tc Source ThreadContext.
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*/
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void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
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#endif
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