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gem5/src/arch/riscv
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Brandon Potter a928a438b8 style: [patch 3/22] reduce include dependencies in some headers 
Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.
2016-11-09 14:27:40 -06:00
..
isa riscv: [Patch 7/5] Corrected LRSC semantics 2016-11-30 17:10:28 -05:00
linux syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc 2016-11-09 14:27:40 -06:00
decoder.cc arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
decoder.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
faults.cc riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD 2016-11-30 17:10:28 -05:00
faults.hh riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD 2016-11-30 17:10:28 -05:00
idle_event.cc arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
idle_event.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
interrupts.cc arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
interrupts.hh style: [patch 3/22] reduce include dependencies in some headers 2016-11-09 14:27:40 -06:00
isa.cc arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
isa.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
isa_traits.hh riscv: [Patch 5/5] Added missing support for timing CPU models 2016-11-30 17:10:28 -05:00
kernel_stats.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
locked_mem.hh riscv: [Patch 7/5] Corrected LRSC semantics 2016-11-30 17:10:28 -05:00
microcode_rom.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
mmapped_ipr.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
pagetable.cc arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
pagetable.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
pra_constants.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
process.cc style: [patch 3/22] reduce include dependencies in some headers 2016-11-09 14:27:40 -06:00
process.hh style: [patch 3/22] reduce include dependencies in some headers 2016-11-09 14:27:40 -06:00
pseudo_inst.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
registers.hh riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A 2016-11-30 17:10:28 -05:00
remote_gdb.cc arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
remote_gdb.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
RiscvInterrupts.py arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
RiscvISA.py arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
RiscvSystem.py arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
RiscvTLB.py arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
SConscript arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
SConsopts arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
stacktrace.cc arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
stacktrace.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
system.cc arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
system.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
tlb.cc arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
tlb.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
types.hh riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A 2016-11-30 17:10:28 -05:00
utility.hh riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD 2016-11-30 17:10:28 -05:00
vtophys.hh arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00