844fb845a5
currently the PC is incremented on an instruction granularity, and not as an instruction's byte address. machine ISA instructions assume the PC is a byte address, and is incremented accordingly. here we make the GPU model, and the HSAIL instructions treat the PC as a byte address as well.
70 lines
2.5 KiB
C++
70 lines
2.5 KiB
C++
/*
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* Copyright (c) 2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Anthony Gutierrez
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*/
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#ifndef __ARCH_HSAIL_GPU_TYPES_HH__
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#define __ARCH_HSAIL_GPU_TYPES_HH__
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#include <cstdint>
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namespace Brig
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{
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class BrigInstBase;
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}
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class BrigObject;
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namespace HsailISA
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{
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// A raw machine instruction represents the raw bits that
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// our model uses to represent an actual instruction. In
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// the case of HSAIL this is just an index into a list of
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// instruction objects.
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typedef uint32_t RawMachInst;
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// The MachInst is a representation of an instruction
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// that has more information than just the machine code.
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// For HSAIL the actual machine code is a BrigInstBase
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// and the BrigObject contains more pertinent
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// information related to operaands, etc.
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struct MachInst
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{
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const Brig::BrigInstBase *brigInstBase;
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const BrigObject *brigObj;
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};
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}
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#endif // __ARCH_HSAIL_GPU_TYPES_HH__
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