0deef376d9
This patch includes software engineering changes and some generic bug fixes
Joel Hestness and Yasuko Eckert made to McPAT 0.8. There are still known
issues/concernts we did not have a chance to address in this patch.
High-level changes in this patch include:
1) Making XML parsing modular and hierarchical:
- Shift parsing responsibility into the components
- Read XML in a (mostly) context-free recursive manner so that McPAT input
files can contain arbitrary component hierarchies
2) Making power, energy, and area calculations a hierarchical and recursive
process
- Components track their subcomponents and recursively call compute
functions in stages
- Make C++ object hierarchy reflect inheritance of classes of components
with similar structures
- Simplify computeArea() and computeEnergy() functions to eliminate
successive calls to calculate separate TDP vs. runtime energy
- Remove Processor component (now unnecessary) and introduce a more abstract
System component
3) Standardizing McPAT output across all components
- Use a single, common data structure for storing and printing McPAT output
- Recursively call print functions through component hierarchy
4) For caches, allow splitting data array and tag array reads and writes for
better accuracy
5) Improving the usability of CACTI by printing more helpful warning and error
messages
6) Minor: Impose more rigorous code style for clarity (more work still to be
done)
Overall, these changes greatly reduce the amount of replicated code, and they
improve McPAT runtime and decrease memory footprint.
614 lines
27 KiB
C++
614 lines
27 KiB
C++
/*****************************************************************************
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* McPAT
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2012 Hewlett-Packard Development Company, L.P.
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* Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#include <algorithm>
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#include <cassert>
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#include <cmath>
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#include <iostream>
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#include <string>
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#include "basic_circuit.h"
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#include "basic_components.h"
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#include "common.h"
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#include "const.h"
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#include "io.h"
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#include "logic.h"
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#include "memoryctrl.h"
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#include "parameter.h"
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/* overview of MC models:
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* McPAT memory controllers are modeled according to large number of industrial data points.
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* The Basic memory controller architecture is base on the Synopsis designs
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* (DesignWare DDR2/DDR3-Lite memory controllers and DDR2/DDR3-Lite protocol controllers)
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* as in Cadence ChipEstimator Tool
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*
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* An MC has 3 parts as shown in this design. McPAT models both high performance MC
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* based on Niagara processor designs and curving and low power MC based on data points in
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* Cadence ChipEstimator Tool.
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*
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* The frontend is modeled analytically, the backend is modeled empirically according to
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* DDR2/DDR3-Lite protocol controllers in Cadence ChipEstimator Tool
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* The PHY is modeled based on
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* "A 100mW 9.6Gb/s Transceiver in 90nm CMOS for next-generation memory interfaces ," ISSCC 2006,
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* and A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communication," ISSCC 2007
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*
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* In Cadence ChipEstimator Tool there are two types of memory controllers: the full memory controllers
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* that includes the frontend as the DesignWare DDR2/DDR3-Lite memory controllers and the backend only
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* memory controllers as the DDR2/DDR3-Lite protocol controllers (except DesignWare DDR2/DDR3-Lite memory
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* controllers, all memory controller IP in Cadence ChipEstimator Tool are backend memory controllers such as
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* DDRC 1600A and DDRC 800A). Thus,to some extend the area and power difference between DesignWare
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* DDR2/DDR3-Lite memory controllers and DDR2/DDR3-Lite protocol controllers can be an estimation to the
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* frontend power and area, which is very close the analitically modeled results of the frontend for Niagara2@65nm
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*
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*/
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MCBackend::MCBackend(XMLNode* _xml_data, InputParameter* interface_ip_,
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const MCParameters & mcp_, const MCStatistics & mcs_)
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: McPATComponent(_xml_data), l_ip(*interface_ip_), mcp(mcp_), mcs(mcs_) {
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name = "Transaction Engine";
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local_result = init_interface(&l_ip, name);
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// Set up stats for the power calculations
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tdp_stats.reset();
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tdp_stats.readAc.access = 0.5 * mcp.num_channels * mcp.clockRate;
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tdp_stats.writeAc.access = 0.5 * mcp.num_channels * mcp.clockRate;
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rtp_stats.reset();
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rtp_stats.readAc.access = mcs.reads;
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rtp_stats.writeAc.access = mcs.writes;
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}
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void MCBackend::computeArea() {
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// The area is in nm^2
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if (mcp.mc_type == MC) {
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if (mcp.type == 0) {
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output_data.area = (2.7927 * log(mcp.peak_transfer_rate * 2) -
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19.862) / 2.0 * mcp.dataBusWidth / 128.0 *
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(l_ip.F_sz_um / 0.09) * mcp.num_channels;
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} else {
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output_data.area = 0.15 * mcp.dataBusWidth / 72.0 *
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(l_ip.F_sz_um / 0.065) * (l_ip.F_sz_um / 0.065) *
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mcp.num_channels;
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}
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} else {
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//skip old model
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cout << "Unknown memory controllers" << endl;
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exit(0);
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//area based on Cadence ChipEstimator for 8bit bus
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output_data.area = 0.243 * mcp.dataBusWidth / 8;
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}
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}
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void MCBackend::computeEnergy() {
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double C_MCB, mc_power;
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double backend_dyn;
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double backend_gates;
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double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio();
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double NMOS_sizing = g_tp.min_w_nmos_;
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double PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r;
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double area_um2 = output_data.area * 1e6;
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if (mcp.mc_type == MC) {
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if (mcp.type == 0) {
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//assuming the approximately same scaling factor as seen in processors.
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//C_MCB = 1.6/200/1e6/144/1.2/1.2*g_ip.F_sz_um/0.19;//Based on Niagara power numbers.The base power (W) is divided by device frequency and vdd and scale to target process.
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//mc_power = 0.0291*2;//29.1mW@200MHz @130nm From Power Analysis of SystemLevel OnChip Communication Architectures by Lahiri et
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mc_power = 4.32*0.1;//4.32W@1GhzMHz @65nm Cadence ChipEstimator 10% for backend
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C_MCB = mc_power/1e9/72/1.1/1.1*l_ip.F_sz_um/0.065;
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//per access energy in memory controller
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power.readOp.dynamic = C_MCB * g_tp.peri_global.Vdd *
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g_tp.peri_global.Vdd *
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(mcp.dataBusWidth/*+mcp.addressBusWidth*/);
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power.readOp.leakage = area_um2 / 2 *
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(g_tp.scaling_factor.core_tx_density) *
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cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
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g_tp.peri_global.Vdd;//unit W
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power.readOp.gate_leakage = area_um2 / 2 *
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(g_tp.scaling_factor.core_tx_density) *
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cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
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g_tp.peri_global.Vdd;//unit W
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} else {
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//Average on DDR2/3 protocol controller and DDRC 1600/800A in
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//Cadence ChipEstimate
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backend_dyn = 0.9e-9 / 800e6 * mcp.clockRate / 12800 *
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mcp.peak_transfer_rate* mcp.dataBusWidth / 72.0 *
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g_tp.peri_global.Vdd / 1.1 * g_tp.peri_global.Vdd / 1.1 *
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(l_ip.F_sz_nm/65.0);
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//Scaling to technology and DIMM feature. The base IP support
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//DDR3-1600(PC3 12800)
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//5000 is from Cadence ChipEstimator
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backend_gates = 50000 * mcp.dataBusWidth / 64.0;
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power.readOp.dynamic = backend_dyn;
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power.readOp.leakage = (backend_gates) *
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cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) *
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g_tp.peri_global.Vdd;//unit W
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power.readOp.gate_leakage = (backend_gates) *
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cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) *
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g_tp.peri_global.Vdd;//unit W
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}
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} else {
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//skip old model
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cout<<"Unknown memory controllers"<<endl;exit(0);
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//mc_power = 4.32*0.1;//4.32W@1GhzMHz @65nm Cadence ChipEstimator 10% for backend
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C_MCB = mc_power/1e9/72/1.1/1.1*l_ip.F_sz_um/0.065;
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power.readOp.leakage = area_um2 / 2 *
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(g_tp.scaling_factor.core_tx_density) *
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cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
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g_tp.peri_global.Vdd;//unit W
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power.readOp.gate_leakage = area_um2 / 2 *
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(g_tp.scaling_factor.core_tx_density) *
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cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
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g_tp.peri_global.Vdd;//unit W
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power.readOp.dynamic *= 1.2;
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power.readOp.leakage *= 1.2;
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power.readOp.gate_leakage *= 1.2;
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//flash controller has about 20% more backend power since BCH ECC in
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//flash is complex and power hungry
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}
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double long_channel_device_reduction =
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longer_channel_device_reduction(Uncore_device);
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power.readOp.longer_channel_leakage = power.readOp.leakage *
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long_channel_device_reduction;
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// Output leakage power calculations
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output_data.subthreshold_leakage_power =
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longer_channel_device ? power.readOp.longer_channel_leakage :
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power.readOp.leakage;
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output_data.gate_leakage_power = power.readOp.gate_leakage;
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// Peak dynamic power calculation
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output_data.peak_dynamic_power = power.readOp.dynamic *
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(tdp_stats.readAc.access + tdp_stats.writeAc.access);
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// Runtime dynamic energy calculation
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output_data.runtime_dynamic_energy =
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power.readOp.dynamic *
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(rtp_stats.readAc.access + rtp_stats.writeAc.access) *
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mcp.llcBlockSize * BITS_PER_BYTE / mcp.dataBusWidth +
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// Original McPAT code: Assume 10% of peak power is consumed by routine
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// job including memory refreshing and scrubbing
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power.readOp.dynamic * 0.1 * execution_time;
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}
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MCPHY::MCPHY(XMLNode* _xml_data, InputParameter* interface_ip_,
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const MCParameters & mcp_, const MCStatistics & mcs_)
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: McPATComponent(_xml_data), l_ip(*interface_ip_), mcp(mcp_), mcs(mcs_) {
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name = "Physical Interface (PHY)";
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local_result = init_interface(&l_ip, name);
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// Set up stats for the power calculations
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// TODO: Figure out why TDP stats aren't used
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tdp_stats.reset();
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tdp_stats.readAc.access = 0.5 * mcp.num_channels;
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tdp_stats.writeAc.access = 0.5 * mcp.num_channels;
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rtp_stats.reset();
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rtp_stats.readAc.access = mcs.reads;
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rtp_stats.writeAc.access = mcs.writes;
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}
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void MCPHY::computeArea() {
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if (mcp.mc_type == MC) {
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if (mcp.type == 0) {
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//Based on die photos from Niagara 1 and 2.
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//TODO merge this into undifferentiated core.PHY only achieves
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//square root of the ideal scaling.
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output_data.area = (6.4323 * log(mcp.peak_transfer_rate * 2) -
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48.134) * mcp.dataBusWidth / 128.0 *
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(l_ip.F_sz_um / 0.09) * mcp.num_channels / 2;//TODO:/2
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} else {
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//Designware/synopsis 16bit DDR3 PHY is 1.3mm (WITH IOs) at 40nm
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//for upto DDR3 2133 (PC3 17066)
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double non_IO_percentage = 0.2;
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output_data.area = 1.3 * non_IO_percentage / 2133.0e6 *
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mcp.clockRate / 17066 * mcp.peak_transfer_rate *
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mcp.dataBusWidth / 16.0 * (l_ip.F_sz_um / 0.040)*
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(l_ip.F_sz_um / 0.040) * mcp.num_channels;//um^2
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}
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} else {
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//area based on Cadence ChipEstimator for 8bit bus
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output_data.area = 0.4e6 / 2 * mcp.dataBusWidth / 8 / 1e6;
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}
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}
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void MCPHY::computeEnergy() {
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//PHY uses internal data buswidth but the actuall off-chip datawidth is 64bits + ecc
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double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio();
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/*
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* according to "A 100mW 9.6Gb/s Transceiver in 90nm CMOS for next-generation memory interfaces ," ISSCC 2006;
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* From Cadence ChipEstimator for normal I/O around 0.4~0.8 mW/Gb/s
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*/
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double power_per_gb_per_s, phy_dyn,phy_gates;
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double NMOS_sizing = g_tp.min_w_nmos_;
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double PMOS_sizing = g_tp.min_w_nmos_ * pmos_to_nmos_sizing_r;
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double area_um2 = output_data.area * 1e6;
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if (mcp.mc_type == MC) {
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if (mcp.type == 0) {
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power_per_gb_per_s = mcp.LVDS ? 0.01 : 0.04;
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//This is from curve fitting based on Niagara 1 and 2's PHY die photo.
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//This is power not energy, 10mw/Gb/s @90nm for each channel and scaling down
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//power.readOp.dynamic = 0.02*memAccesses*llcBlocksize*8;//change from Bytes to bits.
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power.readOp.dynamic = power_per_gb_per_s *
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sqrt(l_ip.F_sz_um / 0.09) * g_tp.peri_global.Vdd / 1.2 *
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g_tp.peri_global.Vdd / 1.2;
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power.readOp.leakage = area_um2 / 2 *
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(g_tp.scaling_factor.core_tx_density) *
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cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
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g_tp.peri_global.Vdd;//unit W
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power.readOp.gate_leakage = area_um2 / 2 *
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(g_tp.scaling_factor.core_tx_density) *
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cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 1, inv) *
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g_tp.peri_global.Vdd;//unit W
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} else {
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phy_gates = 200000 * mcp.dataBusWidth / 64.0;
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power_per_gb_per_s = 0.01;
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//This is power not energy, 10mw/Gb/s @90nm for each channel and scaling down
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power.readOp.dynamic = power_per_gb_per_s * (l_ip.F_sz_um / 0.09) *
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g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd / 1.2;
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power.readOp.leakage = (mcp.withPHY ? phy_gates : 0) *
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cmos_Isub_leakage(NMOS_sizing, PMOS_sizing, 2, nand) *
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g_tp.peri_global.Vdd;//unit W
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power.readOp.gate_leakage = (mcp.withPHY ? phy_gates : 0) *
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cmos_Ig_leakage(NMOS_sizing, PMOS_sizing, 2, nand) *
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g_tp.peri_global.Vdd;//unit W
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}
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}
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// double phy_factor = (int)ceil(mcp.dataBusWidth/72.0);//Previous phy power numbers are based on 72 bit DIMM interface
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// power_t.readOp.dynamic *= phy_factor;
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// power_t.readOp.leakage *= phy_factor;
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// power_t.readOp.gate_leakage *= phy_factor;
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double long_channel_device_reduction =
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longer_channel_device_reduction(Uncore_device);
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power.readOp.longer_channel_leakage =
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power.readOp.leakage * long_channel_device_reduction;
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// Leakage power calculations
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output_data.subthreshold_leakage_power =
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longer_channel_device ? power.readOp.longer_channel_leakage :
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power.readOp.leakage;
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output_data.gate_leakage_power = power.readOp.gate_leakage;
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// Peak dynamic power calculation
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double data_transfer_unit = (mcp.mc_type == MC)? 72:16;/*DIMM data width*/
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output_data.peak_dynamic_power = power.readOp.dynamic *
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(mcp.peak_transfer_rate * BITS_PER_BYTE / 1e3) * mcp.dataBusWidth /
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data_transfer_unit * mcp.num_channels / mcp.clockRate;
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// Runtime dynamic energy calculation
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output_data.runtime_dynamic_energy =
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power.readOp.dynamic *
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(rtp_stats.readAc.access + rtp_stats.writeAc.access) *
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mcp.llcBlockSize * BITS_PER_BYTE / 1e9 +
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// Original McPAT code: Assume 10% of peak power is consumed by routine
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// job including memory refreshing and scrubbing
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power.readOp.dynamic * 0.1 * execution_time;
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}
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MCFrontEnd::MCFrontEnd(XMLNode* _xml_data, InputParameter* interface_ip_,
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const MCParameters & mcp_, const MCStatistics & mcs_)
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: McPATComponent(_xml_data), frontendBuffer(NULL), readBuffer(NULL),
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writeBuffer(NULL), MC_arb(NULL), interface_ip(*interface_ip_),
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mcp(mcp_), mcs(mcs_) {
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int tag, data;
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bool is_default = true;//indication for default setup
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/* MC frontend engine channels share the same engines but logically partitioned
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* For all hardware inside MC. different channels do not share resources.
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* TODO: add docodeing/mux stage to steer memory requests to different channels.
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*/
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name = "Front End";
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// Memory Request Reorder Buffer
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tag = mcp.addressbus_width + EXTRA_TAG_BITS + mcp.opcodeW;
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data = int(ceil((physical_address_width + mcp.opcodeW) / BITS_PER_BYTE));
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interface_ip.cache_sz = data * mcp.req_window_size_per_channel;
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interface_ip.line_sz = data;
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interface_ip.assoc = mcp.reorder_buffer_assoc;
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interface_ip.nbanks = mcp.reorder_buffer_nbanks;
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interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE;
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interface_ip.specific_tag = tag > 0;
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interface_ip.tag_w = tag;
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interface_ip.access_mode = Normal;
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 0;
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interface_ip.num_rd_ports = mcp.num_channels;
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interface_ip.num_wr_ports = interface_ip.num_rd_ports;
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interface_ip.num_se_rd_ports = 0;
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interface_ip.num_search_ports = mcp.num_channels;
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interface_ip.is_cache = true;
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interface_ip.pure_cam = false;
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interface_ip.pure_ram = false;
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interface_ip.throughput = 1.0 / mcp.clockRate;
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interface_ip.latency = 1.0 / mcp.clockRate;
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frontendBuffer = new CacheArray(xml_data, &interface_ip, "Reorder Buffer",
|
|
Uncore_device, mcp.clockRate);
|
|
children.push_back(frontendBuffer);
|
|
|
|
frontendBuffer->tdp_stats.reset();
|
|
frontendBuffer->tdp_stats.readAc.access =
|
|
frontendBuffer->l_ip.num_search_ports +
|
|
frontendBuffer->l_ip.num_wr_ports;
|
|
frontendBuffer->tdp_stats.writeAc.access =
|
|
frontendBuffer->l_ip.num_search_ports;
|
|
frontendBuffer->tdp_stats.searchAc.access =
|
|
frontendBuffer->l_ip.num_wr_ports;
|
|
frontendBuffer->rtp_stats.reset();
|
|
// TODO: These stats assume that access power is calculated per buffer
|
|
// bit, which requires the stats to take into account the number of
|
|
// bits for each buffer slot. This should be revised...
|
|
//For each channel, each memory word need to check the address data to
|
|
//achieve best scheduling results.
|
|
//and this need to be done on all physical DIMMs in each logical memory
|
|
//DIMM *mcp.dataBusWidth/72
|
|
frontendBuffer->rtp_stats.readAc.access = mcs.reads * mcp.llcBlockSize *
|
|
BITS_PER_BYTE / mcp.dataBusWidth * mcp.dataBusWidth / 72;
|
|
frontendBuffer->rtp_stats.writeAc.access = mcs.writes * mcp.llcBlockSize *
|
|
BITS_PER_BYTE / mcp.dataBusWidth * mcp.dataBusWidth / 72;
|
|
frontendBuffer->rtp_stats.searchAc.access =
|
|
frontendBuffer->rtp_stats.readAc.access +
|
|
frontendBuffer->rtp_stats.writeAc.access;
|
|
|
|
// Read Buffers
|
|
//Support key words first operation
|
|
data = (int)ceil(mcp.dataBusWidth / BITS_PER_BYTE);
|
|
|
|
interface_ip.cache_sz = data * mcp.IO_buffer_size_per_channel;
|
|
interface_ip.line_sz = data;
|
|
interface_ip.assoc = mcp.read_buffer_assoc;
|
|
interface_ip.nbanks = mcp.read_buffer_nbanks;
|
|
interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE;
|
|
interface_ip.specific_tag = mcp.read_buffer_tag_width > 0;
|
|
interface_ip.tag_w = mcp.read_buffer_tag_width;
|
|
interface_ip.access_mode = Sequential;
|
|
interface_ip.obj_func_dyn_energy = 0;
|
|
interface_ip.obj_func_dyn_power = 0;
|
|
interface_ip.obj_func_leak_power = 0;
|
|
interface_ip.obj_func_cycle_t = 1;
|
|
interface_ip.num_rw_ports = 0;
|
|
interface_ip.num_rd_ports = mcp.num_channels;
|
|
interface_ip.num_wr_ports = interface_ip.num_rd_ports;
|
|
interface_ip.num_se_rd_ports = 0;
|
|
interface_ip.num_search_ports = 0;
|
|
interface_ip.is_cache = false;
|
|
interface_ip.pure_cam = false;
|
|
interface_ip.pure_ram = true;
|
|
interface_ip.throughput = 1.0 / mcp.clockRate;
|
|
interface_ip.latency = 1.0 / mcp.clockRate;
|
|
readBuffer = new CacheArray(xml_data, &interface_ip, "Read Buffer",
|
|
Uncore_device, mcp.clockRate);
|
|
children.push_back(readBuffer);
|
|
|
|
readBuffer->tdp_stats.reset();
|
|
readBuffer->tdp_stats.readAc.access = readBuffer->l_ip.num_rd_ports *
|
|
mcs.duty_cycle;
|
|
readBuffer->tdp_stats.writeAc.access = readBuffer->l_ip.num_wr_ports *
|
|
mcs.duty_cycle;
|
|
readBuffer->rtp_stats.reset();
|
|
readBuffer->rtp_stats.readAc.access = mcs.reads * mcp.llcBlockSize *
|
|
BITS_PER_BYTE / mcp.dataBusWidth;
|
|
readBuffer->rtp_stats.writeAc.access = mcs.reads * mcp.llcBlockSize *
|
|
BITS_PER_BYTE / mcp.dataBusWidth;
|
|
|
|
// Write Buffer
|
|
//Support key words first operation
|
|
data = (int)ceil(mcp.dataBusWidth / BITS_PER_BYTE);
|
|
|
|
interface_ip.cache_sz = data * mcp.IO_buffer_size_per_channel;
|
|
interface_ip.line_sz = data;
|
|
interface_ip.assoc = mcp.write_buffer_assoc;
|
|
interface_ip.nbanks = mcp.write_buffer_nbanks;
|
|
interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE;
|
|
interface_ip.specific_tag = mcp.write_buffer_tag_width > 0;
|
|
interface_ip.tag_w = mcp.write_buffer_tag_width;
|
|
interface_ip.access_mode = Normal;
|
|
interface_ip.obj_func_dyn_energy = 0;
|
|
interface_ip.obj_func_dyn_power = 0;
|
|
interface_ip.obj_func_leak_power = 0;
|
|
interface_ip.obj_func_cycle_t = 1;
|
|
interface_ip.num_rw_ports = 0;
|
|
interface_ip.num_rd_ports = mcp.num_channels;
|
|
interface_ip.num_wr_ports = interface_ip.num_rd_ports;
|
|
interface_ip.num_se_rd_ports = 0;
|
|
interface_ip.num_search_ports = 0;
|
|
interface_ip.is_cache = false;
|
|
interface_ip.pure_cam = false;
|
|
interface_ip.pure_ram = true;
|
|
interface_ip.throughput = 1.0 / mcp.clockRate;
|
|
interface_ip.latency = 1.0 / mcp.clockRate;
|
|
writeBuffer = new CacheArray(xml_data, &interface_ip, "Write Buffer",
|
|
Uncore_device, mcp.clockRate);
|
|
children.push_back(writeBuffer);
|
|
|
|
writeBuffer->tdp_stats.reset();
|
|
writeBuffer->tdp_stats.readAc.access = writeBuffer->l_ip.num_rd_ports *
|
|
mcs.duty_cycle;
|
|
writeBuffer->tdp_stats.writeAc.access = writeBuffer->l_ip.num_wr_ports *
|
|
mcs.duty_cycle;
|
|
writeBuffer->rtp_stats.reset();
|
|
writeBuffer->rtp_stats.readAc.access = mcs.reads * mcp.llcBlockSize *
|
|
BITS_PER_BYTE / mcp.dataBusWidth;
|
|
writeBuffer->rtp_stats.writeAc.access = mcs.writes * mcp.llcBlockSize *
|
|
BITS_PER_BYTE / mcp.dataBusWidth;
|
|
|
|
// TODO: Set up selection logic as a leaf node in tree
|
|
//selection and arbitration logic
|
|
MC_arb =
|
|
new selection_logic(xml_data, is_default,
|
|
mcp.req_window_size_per_channel, 1, &interface_ip,
|
|
"Arbitration Logic", (mcs.reads + mcs.writes),
|
|
mcp.clockRate, Uncore_device);
|
|
// MC_arb is not included in the roll-up due to the uninitialized area
|
|
//children.push_back(MC_arb);
|
|
}
|
|
|
|
MemoryController::MemoryController(XMLNode* _xml_data,
|
|
InputParameter* interface_ip_)
|
|
: McPATComponent(_xml_data), interface_ip(*interface_ip_) {
|
|
name = "Memory Controller";
|
|
set_mc_param();
|
|
// TODO: Pass params and stats as pointers
|
|
children.push_back(new MCFrontEnd(xml_data, &interface_ip, mcp, mcs));
|
|
children.push_back(new MCBackend(xml_data, &interface_ip, mcp, mcs));
|
|
|
|
if (mcp.type==0 || (mcp.type == 1 && mcp.withPHY)) {
|
|
children.push_back(new MCPHY(xml_data, &interface_ip, mcp, mcs));
|
|
}
|
|
}
|
|
|
|
void MemoryController::initialize_params() {
|
|
memset(&mcp, 0, sizeof(MCParameters));
|
|
}
|
|
|
|
void MemoryController::set_mc_param() {
|
|
initialize_params();
|
|
|
|
int num_children = xml_data->nChildNode("param");
|
|
int tech_type;
|
|
int mat_type;
|
|
int i;
|
|
for (i = 0; i < num_children; i++) {
|
|
XMLNode* paramNode = xml_data->getChildNodePtr("param", &i);
|
|
XMLCSTR node_name = paramNode->getAttribute("name");
|
|
XMLCSTR value = paramNode->getAttribute("value");
|
|
|
|
if (!node_name)
|
|
warnMissingParamName(paramNode->getAttribute("id"));
|
|
|
|
ASSIGN_FP_IF("mc_clock", mcp.clockRate);
|
|
ASSIGN_INT_IF("tech_type", tech_type);
|
|
ASSIGN_ENUM_IF("mc_type", mcp.mc_type, MemoryCtrl_type);
|
|
ASSIGN_FP_IF("num_mcs", mcp.num_mcs);
|
|
ASSIGN_INT_IF("llc_line_length", mcp.llc_line_length);
|
|
ASSIGN_INT_IF("databus_width", mcp.databus_width);
|
|
ASSIGN_INT_IF("memory_channels_per_mc", mcp.num_channels);
|
|
ASSIGN_INT_IF("req_window_size_per_channel",
|
|
mcp.req_window_size_per_channel);
|
|
ASSIGN_INT_IF("IO_buffer_size_per_channel",
|
|
mcp.IO_buffer_size_per_channel);
|
|
ASSIGN_INT_IF("addressbus_width", mcp.addressbus_width);
|
|
ASSIGN_INT_IF("opcode_width", mcp.opcodeW);
|
|
ASSIGN_INT_IF("type", mcp.type);
|
|
ASSIGN_ENUM_IF("LVDS", mcp.LVDS, bool);
|
|
ASSIGN_ENUM_IF("withPHY", mcp.withPHY, bool);
|
|
ASSIGN_INT_IF("peak_transfer_rate", mcp.peak_transfer_rate);
|
|
ASSIGN_INT_IF("number_ranks", mcp.number_ranks);
|
|
ASSIGN_INT_IF("reorder_buffer_assoc", mcp.reorder_buffer_assoc);
|
|
ASSIGN_INT_IF("reorder_buffer_nbanks", mcp.reorder_buffer_nbanks);
|
|
ASSIGN_INT_IF("read_buffer_assoc", mcp.read_buffer_assoc);
|
|
ASSIGN_INT_IF("read_buffer_nbanks", mcp.read_buffer_nbanks);
|
|
ASSIGN_INT_IF("read_buffer_tag_width", mcp.read_buffer_tag_width);
|
|
ASSIGN_INT_IF("write_buffer_assoc", mcp.write_buffer_assoc);
|
|
ASSIGN_INT_IF("write_buffer_nbanks", mcp.write_buffer_nbanks);
|
|
ASSIGN_INT_IF("write_buffer_tag_width", mcp.write_buffer_tag_width);
|
|
ASSIGN_INT_IF("wire_mat_type", mat_type);
|
|
ASSIGN_ENUM_IF("wire_type", interface_ip.wt, Wire_type);
|
|
|
|
else {
|
|
warnUnrecognizedParam(node_name);
|
|
}
|
|
}
|
|
|
|
if (mcp.mc_type != MC) {
|
|
cout << "Unknown memory controller type: Only DRAM controller is "
|
|
<< "supported for now" << endl;
|
|
exit(0);
|
|
}
|
|
|
|
// Change from MHz to Hz
|
|
mcp.clockRate *= 1e6;
|
|
|
|
interface_ip.data_arr_ram_cell_tech_type = tech_type;
|
|
interface_ip.data_arr_peri_global_tech_type = tech_type;
|
|
interface_ip.tag_arr_ram_cell_tech_type = tech_type;
|
|
interface_ip.tag_arr_peri_global_tech_type = tech_type;
|
|
interface_ip.wire_is_mat_type = mat_type;
|
|
interface_ip.wire_os_mat_type = mat_type;
|
|
|
|
num_children = xml_data->nChildNode("stat");
|
|
for (i = 0; i < num_children; i++) {
|
|
XMLNode* statNode = xml_data->getChildNodePtr("stat", &i);
|
|
XMLCSTR node_name = statNode->getAttribute("name");
|
|
XMLCSTR value = statNode->getAttribute("value");
|
|
|
|
if (!node_name)
|
|
warnMissingStatName(statNode->getAttribute("id"));
|
|
|
|
ASSIGN_FP_IF("duty_cycle", mcs.duty_cycle);
|
|
ASSIGN_FP_IF("perc_load", mcs.perc_load);
|
|
ASSIGN_FP_IF("memory_reads", mcs.reads);
|
|
ASSIGN_INT_IF("memory_writes", mcs.writes);
|
|
|
|
else {
|
|
warnUnrecognizedStat(node_name);
|
|
}
|
|
}
|
|
|
|
// Add ECC overhead
|
|
mcp.llcBlockSize = int(ceil(mcp.llc_line_length / BITS_PER_BYTE)) +
|
|
mcp.llc_line_length;
|
|
mcp.dataBusWidth = int(ceil(mcp.databus_width / BITS_PER_BYTE)) +
|
|
mcp.databus_width;
|
|
}
|
|
|
|
MCFrontEnd ::~MCFrontEnd() {
|
|
|
|
if (MC_arb) {
|
|
delete MC_arb;
|
|
MC_arb = NULL;
|
|
}
|
|
if (frontendBuffer) {
|
|
delete frontendBuffer;
|
|
frontendBuffer = NULL;
|
|
}
|
|
if (readBuffer) {
|
|
delete readBuffer;
|
|
readBuffer = NULL;
|
|
}
|
|
if (writeBuffer) {
|
|
delete writeBuffer;
|
|
writeBuffer = NULL;
|
|
}
|
|
}
|
|
|
|
MemoryController::~MemoryController() {
|
|
// TODO: use default constructor to delete children
|
|
}
|
|
|