0deef376d9
This patch includes software engineering changes and some generic bug fixes
Joel Hestness and Yasuko Eckert made to McPAT 0.8. There are still known
issues/concernts we did not have a chance to address in this patch.
High-level changes in this patch include:
1) Making XML parsing modular and hierarchical:
- Shift parsing responsibility into the components
- Read XML in a (mostly) context-free recursive manner so that McPAT input
files can contain arbitrary component hierarchies
2) Making power, energy, and area calculations a hierarchical and recursive
process
- Components track their subcomponents and recursively call compute
functions in stages
- Make C++ object hierarchy reflect inheritance of classes of components
with similar structures
- Simplify computeArea() and computeEnergy() functions to eliminate
successive calls to calculate separate TDP vs. runtime energy
- Remove Processor component (now unnecessary) and introduce a more abstract
System component
3) Standardizing McPAT output across all components
- Use a single, common data structure for storing and printing McPAT output
- Recursively call print functions through component hierarchy
4) For caches, allow splitting data array and tag array reads and writes for
better accuracy
5) Improving the usability of CACTI by printing more helpful warning and error
messages
6) Minor: Impose more rigorous code style for clarity (more work still to be
done)
Overall, these changes greatly reduce the amount of replicated code, and they
improve McPAT runtime and decrease memory footprint.
180 lines
6.9 KiB
C++
180 lines
6.9 KiB
C++
/*****************************************************************************
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* McPAT
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* SOFTWARE LICENSE AGREEMENT
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* Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Joel Hestness
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*
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***************************************************************************/
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#include <algorithm>
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#include <cassert>
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#include <cmath>
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#include <iostream>
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#include <string>
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#include "basic_circuit.h"
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#include "bus_interconnect.h"
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#include "common.h"
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#include "const.h"
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#include "io.h"
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#include "parameter.h"
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BusInterconnect::BusInterconnect(XMLNode* _xml_data,
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InputParameter* interface_ip_)
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: McPATComponent(_xml_data), link_bus(NULL), interface_ip(*interface_ip_) {
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name = "Bus Interconnect";
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set_param_stats();
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local_result = init_interface(&interface_ip, name);
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scktRatio = g_tp.sckt_co_eff;
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interface_ip.throughput = bus_params.link_throughput / bus_params.clockRate;
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interface_ip.latency = bus_params.link_latency / bus_params.clockRate;
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link_len /= bus_params.total_nodes;
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if (bus_params.total_nodes > 1) {
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//All links are shared by neighbors
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link_len /= 2;
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}
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link_bus = new Interconnect(xml_data, "Link", Uncore_device,
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bus_params.link_base_width,
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bus_params.link_base_height,
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bus_params.flit_size, link_len, &interface_ip,
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bus_params.link_start_wiring_level,
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bus_params.clockRate,
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bus_params.pipelinable,
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bus_params.route_over_perc);
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children.push_back(link_bus);
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}
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void BusInterconnect::computeEnergy() {
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// Initialize stats for TDP
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tdp_stats.reset();
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tdp_stats.readAc.access = bus_stats.duty_cycle;
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link_bus->int_params.active_ports = bus_params.min_ports - 1;
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link_bus->int_stats.duty_cycle =
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bus_params.M_traffic_pattern * bus_stats.duty_cycle;
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// Initialize stats for runtime energy and power
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rtp_stats.reset();
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rtp_stats.readAc.access = bus_stats.total_access;
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link_bus->int_stats.accesses = bus_stats.total_access;
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// Recursively compute energy
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McPATComponent::computeEnergy();
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}
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void BusInterconnect::set_param_stats() {
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memset(&bus_params, 0, sizeof(BusInterconnectParameters));
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int num_children = xml_data->nChildNode("param");
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int i;
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int mat_type;
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for (i = 0; i < num_children; i++) {
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XMLNode* paramNode = xml_data->getChildNodePtr("param", &i);
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XMLCSTR node_name = paramNode->getAttribute("name");
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XMLCSTR value = paramNode->getAttribute("value");
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if (!node_name)
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warnMissingParamName(paramNode->getAttribute("id"));
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ASSIGN_FP_IF("clockrate", bus_params.clockRate);
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ASSIGN_INT_IF("flit_bits", bus_params.flit_size);
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ASSIGN_FP_IF("link_throughput", bus_params.link_throughput);
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ASSIGN_FP_IF("link_latency", bus_params.link_latency);
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ASSIGN_INT_IF("total_nodes", bus_params.total_nodes);
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ASSIGN_INT_IF("input_ports", bus_params.input_ports);
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ASSIGN_INT_IF("output_ports", bus_params.output_ports);
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ASSIGN_INT_IF("global_linked_ports", bus_params.global_linked_ports);
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ASSIGN_FP_IF("chip_coverage", bus_params.chip_coverage);
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ASSIGN_INT_IF("pipelinable", bus_params.pipelinable);
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ASSIGN_FP_IF("link_routing_over_percentage",
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bus_params.route_over_perc);
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ASSIGN_INT_IF("virtual_channel_per_port",
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bus_params.virtual_channel_per_port);
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ASSIGN_FP_IF("M_traffic_pattern", bus_params.M_traffic_pattern);
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ASSIGN_FP_IF("link_len", link_len);
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ASSIGN_FP_IF("link_base_width", bus_params.link_base_width);
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ASSIGN_FP_IF("link_base_height", bus_params.link_base_height);
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ASSIGN_FP_IF("link_start_wiring_level",
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bus_params.link_start_wiring_level);
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ASSIGN_INT_IF("wire_mat_type", mat_type);
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ASSIGN_ENUM_IF("wire_type", interface_ip.wt, Wire_type);
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else {
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warnUnrecognizedParam(node_name);
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}
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}
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// Change from MHz to Hz
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bus_params.clockRate *= 1e6;
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interface_ip.wire_is_mat_type = mat_type;
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interface_ip.wire_os_mat_type = mat_type;
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num_children = xml_data->nChildNode("stat");
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for (i = 0; i < num_children; i++) {
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XMLNode* statNode = xml_data->getChildNodePtr("stat", &i);
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XMLCSTR node_name = statNode->getAttribute("name");
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XMLCSTR value = statNode->getAttribute("value");
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if (!node_name)
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warnMissingStatName(statNode->getAttribute("id"));
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ASSIGN_FP_IF("duty_cycle", bus_stats.duty_cycle);
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ASSIGN_FP_IF("total_accesses", bus_stats.total_access);
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else {
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warnUnrecognizedStat(node_name);
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}
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}
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clockRate = bus_params.clockRate;
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bus_params.min_ports =
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min(bus_params.input_ports, bus_params.output_ports);
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assert(bus_params.chip_coverage <= 1);
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assert(bus_params.route_over_perc <= 1);
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assert(link_len > 0);
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}
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void
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BusInterconnect::set_duty_cycle(double duty_cycle) {
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bus_stats.duty_cycle = duty_cycle;
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}
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void
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BusInterconnect::set_number_of_accesses(double total_accesses) {
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bus_stats.total_access = total_accesses;
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}
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BusInterconnect::~BusInterconnect() {
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delete link_bus;
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link_bus = NULL;
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}
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