---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBHits 11837684 # Number of BTB hits global.BPredUnit.BTBLookups 15197122 # Number of BTB lookups global.BPredUnit.RASInCorrect 1217 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 1998573 # Number of conditional branches incorrect global.BPredUnit.condPredicted 12917224 # Number of conditional branches predicted global.BPredUnit.lookups 17533197 # Number of BP lookups global.BPredUnit.usedRAS 1687018 # Number of times the RAS was used to get a target. host_inst_rate 57997 # Simulator instruction rate (inst/s) host_mem_usage 178748 # Number of bytes of host memory used host_seconds 1423.90 # Real time elapsed on the host host_tick_rate 73521 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 10104667 # Number of conflicting loads. memdepunit.memDep.conflictingStores 3292311 # Number of conflicting stores. memdepunit.memDep.insertedLoads 29530804 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 9370879 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 82582323 # Number of instructions simulated sim_seconds 0.000105 # Number of seconds simulated sim_ticks 104686099 # Number of ticks simulated system.cpu.commit.COM:branches 10071057 # Number of branches committed system.cpu.commit.COM:bw_lim_events 3175901 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.samples 65490840 system.cpu.commit.COM:committed_per_cycle.min_value 0 0 32034998 4891.52% 1 13785472 2104.95% 2 8057025 1230.25% 3 3669149 560.25% 4 1988059 303.56% 5 1377349 210.31% 6 785420 119.93% 7 617467 94.28% 8 3175901 484.94% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 90187947 # Number of instructions committed system.cpu.commit.COM:loads 19613586 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 25981086 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 1985168 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 90187947 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 387 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 40679620 # The number of squashed insts skipped by commit system.cpu.committedInsts 82582323 # Number of Instructions Simulated system.cpu.committedInsts_total 82582323 # Number of Instructions Simulated system.cpu.cpi 1.267657 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.267657 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 22673452 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 5439.841232 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4838.693712 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 22672608 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 4591226 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 2385476 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 493 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6365908 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 5074.130393 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4849.051425 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6360739 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 26228180 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000812 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 5169 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 3555 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 7826369 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000254 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1614 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 2811.600000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 3114.692857 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 13779.471761 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 700 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 28116 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 2180285 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 29039360 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 5125.462498 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency system.cpu.dcache.demand_hits 29033347 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 30819406 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000207 # miss rate for demand accesses system.cpu.dcache.demand_misses 6013 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 3906 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 10211845 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000073 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2107 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 29039360 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 5125.462498 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 29033347 # number of overall hits system.cpu.dcache.overall_miss_latency 30819406 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000207 # miss rate for overall accesses system.cpu.dcache.overall_misses 6013 # number of overall misses system.cpu.dcache.overall_mshr_hits 3906 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 10211845 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000073 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2107 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 104 # number of replacements system.cpu.dcache.sampled_refs 2107 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 1404.053454 # Cycle average of tags in use system.cpu.dcache.total_refs 29033347 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 75 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 2221252 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 13564 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 2815361 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 145659694 # Number of instructions handled by decode system.cpu.decode.DECODE:IdleCycles 36080141 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 27108364 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 6243203 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 50032 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 81084 # Number of cycles decode is unblocking system.cpu.fetch.Branches 17533197 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 17509399 # Number of cache lines fetched system.cpu.fetch.Cycles 45531133 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 484323 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 150299775 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 2040341 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.244419 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 17509399 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 13524702 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.095236 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 71734044 system.cpu.fetch.rateDist.min_value 0 0 43713095 6093.77% 1 2792314 389.26% 2 2129360 296.84% 3 3194083 445.27% 4 4028588 561.60% 5 1363321 190.05% 6 1870461 260.75% 7 1629807 227.20% 8 11013015 1535.26% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist system.cpu.icache.ReadReq_accesses 17509399 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 3388.211547 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 2494.269154 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 17495889 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 45774738 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000772 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 13510 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 3486 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 25002554 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 10024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets 3400.454545 # average number of cycles each access was blocked system.cpu.icache.avg_refs 1745.399940 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 22 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 74810 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 17509399 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 3388.211547 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency system.cpu.icache.demand_hits 17495889 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 45774738 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000772 # miss rate for demand accesses system.cpu.icache.demand_misses 13510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 3486 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 25002554 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 10024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 17509399 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 3388.211547 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 17495889 # number of overall hits system.cpu.icache.overall_miss_latency 45774738 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000772 # miss rate for overall accesses system.cpu.icache.overall_misses 13510 # number of overall misses system.cpu.icache.overall_mshr_hits 3486 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 25002554 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 10024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 8115 # number of replacements system.cpu.icache.sampled_refs 10024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 1481.631027 # Cycle average of tags in use system.cpu.icache.total_refs 17495889 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 32952056 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 12456785 # Number of branches executed system.cpu.iew.EXEC:nop 11559797 # number of nop insts executed system.cpu.iew.EXEC:rate 1.365191 # Inst execution rate system.cpu.iew.EXEC:refs 30958353 # number of memory reference insts executed system.cpu.iew.EXEC:stores 7006627 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.WB:consumers 86914579 # num instructions consuming a value system.cpu.iew.WB:count 96291361 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.729319 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 63388475 # num instructions producing a value system.cpu.iew.WB:rate 1.342338 # insts written-back per cycle system.cpu.iew.WB:sent 96947832 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2153450 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 156060 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 29530804 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 2057217 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 9370879 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 130866464 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 23951726 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 2095770 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 97930658 # Number of executed instructions system.cpu.iew.iewIQFullEvents 43929 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 720 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 6243203 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 62133 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 9874 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 40553 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 855538 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3321 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 18493 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 9874 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 9917218 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 3003379 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 18493 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1143572 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1009878 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.788857 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.788857 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 100026428 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 7 0.00% # Type of FU issued IntAlu 61666427 61.65% # Type of FU issued IntMult 468908 0.47% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2704055 2.70% # Type of FU issued FloatCmp 112834 0.11% # Type of FU issued FloatCvt 2307257 2.31% # Type of FU issued FloatMult 295394 0.30% # Type of FU issued FloatDiv 735688 0.74% # Type of FU issued FloatSqrt 122 0.00% # Type of FU issued MemRead 24586382 24.58% # Type of FU issued MemWrite 7149354 7.15% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 1620744 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 195067 12.04% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 1678 0.10% # attempts to use FU when none available FloatCmp 197 0.01% # attempts to use FU when none available FloatCvt 4552 0.28% # attempts to use FU when none available FloatMult 2392 0.15% # attempts to use FU when none available FloatDiv 951463 58.71% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available MemRead 401417 24.77% # attempts to use FU when none available MemWrite 63978 3.95% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 71734044 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 0 28631398 3991.33% 1 15448994 2153.65% 2 12333631 1719.36% 3 7046540 982.31% 4 4503539 627.81% 5 2295007 319.93% 6 1113179 155.18% 7 291761 40.67% 8 69995 9.76% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.394407 # Inst issue rate system.cpu.iq.iqInstsAdded 119306230 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 100026428 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 35838359 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 150449 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 30462150 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 12131 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 3919.717352 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2067.943230 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 7146 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 19539791 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.410931 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4985 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 10308697 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.410931 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4985 # number of ReadReq MSHR misses system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 75 # number of WriteReqNoAck|Writeback accesses(hits+misses) system.cpu.l2cache.WriteReqNoAck|Writeback_hits 75 # number of WriteReqNoAck|Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 1.448546 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 12131 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 3919.717352 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency system.cpu.l2cache.demand_hits 7146 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 19539791 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.410931 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4985 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 10308697 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.410931 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4985 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 12206 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 3919.717352 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 7221 # number of overall hits system.cpu.l2cache.overall_miss_latency 19539791 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.408406 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4985 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 10308697 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.408406 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4985 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4985 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 3244.539242 # Cycle average of tags in use system.cpu.l2cache.total_refs 7221 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 71734044 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 969328 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 67122956 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 411688 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IdleCycles 37058676 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 742595 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full system.cpu.rename.RENAME:RenameLookups 181728449 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 141044897 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 103457127 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 26196123 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 6243203 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 1187915 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 36334171 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 78799 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 513 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 2731208 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 502 # count of temporary serializing insts renamed system.cpu.timesIdled 10186 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 387 # Number of system calls ---------- End Simulation Statistics ----------