---------- Begin Simulation Statistics ---------- host_inst_rate 953941 # Simulator instruction rate (inst/s) host_mem_usage 204484 # Number of bytes of host memory used host_seconds 4877.84 # Real time elapsed on the host host_tick_rate 1564863626 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176258 # Number of instructions simulated sim_seconds 7.633159 # Number of seconds simulated sim_ticks 7633159262000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1668242528 # number of overall hits system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses system.cpu.dcache.overall_misses 9470550 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 9108982 # number of replacements system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 4084.359780 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 78018940000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244013 # number of writebacks system.cpu.icache.ReadReq_accesses 5658328114 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5658327439 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.icache.avg_refs 8382707.317037 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658328114 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.demand_hits 5658327439 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 675 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658328114 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5658327439 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 675 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 555.303019 # Cycle average of tags in use system.cpu.icache.total_refs 5658327439 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5328546 # number of overall hits system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses system.cpu.l2cache.overall_misses 3785207 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 2772128 # number of replacements system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 25736.997763 # Cycle average of tags in use system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 6030002809000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 15266318524 # number of cpu cycles simulated system.cpu.num_insts 4653176258 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls ---------- End Simulation Statistics ----------