---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBHits 2657 # Number of BTB hits global.BPredUnit.BTBLookups 6786 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 1999 # Number of conditional branches incorrect global.BPredUnit.condPredicted 7531 # Number of conditional branches predicted global.BPredUnit.lookups 7531 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. host_inst_rate 57578 # Simulator instruction rate (inst/s) host_mem_usage 198128 # Number of bytes of host memory used host_seconds 0.19 # Real time elapsed on the host host_tick_rate 76965798 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. memdepunit.memDep.insertedLoads 3022 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 2929 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 10976 # Number of instructions simulated sim_seconds 0.000015 # Number of seconds simulated sim_ticks 14690000 # Number of ticks simulated system.cpu.commit.COM:branches 2152 # Number of branches committed system.cpu.commit.COM:bw_lim_events 93 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.samples 26502 system.cpu.commit.COM:committed_per_cycle.min_value 0 0 20989 7919.78% 1 3011 1136.14% 2 1202 453.55% 3 588 221.87% 4 307 115.84% 5 82 30.94% 6 195 73.58% 7 35 13.21% 8 93 35.09% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 10976 # Number of instructions committed system.cpu.commit.COM:loads 1462 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2760 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 1999 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 329 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 13065 # The number of squashed insts skipped by commit system.cpu.committedInsts 10976 # Number of Instructions Simulated system.cpu.committedInsts_total 10976 # Number of Instructions Simulated system.cpu.cpi 2.675656 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.675656 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 2253 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 9417.910448 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5611.940299 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 2186 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 631000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.029738 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 67 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 376000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.029738 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1171 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 16509.523810 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5709.523810 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1066 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 1733500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089667 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 121 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 599500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089667 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.dcache.avg_refs 21.418301 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 3424 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 13747.093023 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5671.511628 # average overall mshr miss latency system.cpu.dcache.demand_hits 3252 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 2364500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.050234 # miss rate for demand accesses system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 141 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 975500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.050234 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 172 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 3424 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 13747.093023 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5671.511628 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 3252 # number of overall hits system.cpu.dcache.overall_miss_latency 2364500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.050234 # miss rate for overall accesses system.cpu.dcache.overall_misses 172 # number of overall misses system.cpu.dcache.overall_mshr_hits 141 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 975500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.050234 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 172 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 153 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 112.521037 # Cycle average of tags in use system.cpu.dcache.total_refs 3277 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 4038 # Number of cycles decode is blocked system.cpu.decode.DECODE:DecodedInsts 37564 # Number of instructions handled by decode system.cpu.decode.DECODE:IdleCycles 12395 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 10006 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 2866 # Number of cycles decode is squashing system.cpu.decode.DECODE:UnblockCycles 63 # Number of cycles decode is unblocking system.cpu.fetch.Branches 7531 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 4872 # Number of cache lines fetched system.cpu.fetch.Cycles 15997 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 41653 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 2060 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.256436 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 4872 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 2657 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.418312 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 29368 system.cpu.fetch.rateDist.min_value 0 0 18244 6212.20% 1 4822 1641.92% 2 611 208.05% 3 702 239.04% 4 788 268.32% 5 623 212.14% 6 599 203.96% 7 190 64.70% 8 2789 949.67% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist system.cpu.icache.ReadReq_accesses 4851 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 7514.784946 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 5338.709677 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 4479 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 2795500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.076685 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 372 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 1986000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.076685 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 372 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.icache.avg_refs 12.040323 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 4851 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 7514.784946 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 5338.709677 # average overall mshr miss latency system.cpu.icache.demand_hits 4479 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 2795500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.076685 # miss rate for demand accesses system.cpu.icache.demand_misses 372 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 1986000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.076685 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 4851 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 7514.784946 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 5338.709677 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4479 # number of overall hits system.cpu.icache.overall_miss_latency 2795500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.076685 # miss rate for overall accesses system.cpu.icache.overall_misses 372 # number of overall misses system.cpu.icache.overall_mshr_hits 21 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 1986000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.076685 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 372 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 372 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 236.918934 # Cycle average of tags in use system.cpu.icache.total_refs 4479 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 8496 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 3046 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed system.cpu.iew.EXEC:rate 0.623842 # Inst execution rate system.cpu.iew.EXEC:refs 4481 # number of memory reference insts executed system.cpu.iew.EXEC:stores 2103 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.WB:consumers 9128 # num instructions consuming a value system.cpu.iew.WB:count 17742 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.828330 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 7561 # num instructions producing a value system.cpu.iew.WB:rate 0.604127 # insts written-back per cycle system.cpu.iew.WB:sent 17903 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2179 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 3022 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 611 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 2901 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 2929 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 24042 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 2378 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3319 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 18321 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 2866 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 1560 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 1631 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 684 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1495 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.373740 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.373740 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 21640 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 1766 8.16% # Type of FU issued IntAlu 14389 66.49% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued MemRead 2855 13.19% # Type of FU issued MemWrite 2630 12.15% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.008364 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 43 23.76% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available MemRead 23 12.71% # attempts to use FU when none available MemWrite 115 63.54% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 29368 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 0 20067 6832.95% 1 3826 1302.78% 2 2129 724.94% 3 1515 515.87% 4 870 296.24% 5 480 163.44% 6 307 104.54% 7 103 35.07% 8 71 24.18% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 0.736856 # Inst issue rate system.cpu.iq.iqInstsAdded 23431 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 21640 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 611 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 11038 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 7964 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 86 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 4430.232558 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2430.232558 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_miss_latency 381000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 86 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 209000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 86 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 439 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 4291.954023 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2291.954023 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 1867000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990888 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 435 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 997000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990888 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 435 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 4421.052632 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2421.052632 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_miss_latency 84000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.009615 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 525 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 4314.779271 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2314.779271 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 2248000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.992381 # miss rate for demand accesses system.cpu.l2cache.demand_misses 521 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 1206000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.992381 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 521 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 525 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 4314.779271 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2314.779271 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits system.cpu.l2cache.overall_miss_latency 2248000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992381 # miss rate for overall accesses system.cpu.l2cache.overall_misses 521 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 1206000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.992381 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 521 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 263.558349 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 29368 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 13747 # Number of cycles rename is idle system.cpu.rename.RENAME:RenameLookups 51214 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 29558 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 24111 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 8739 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 2866 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 230 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 14243 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 3786 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 643 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 4459 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 681 # count of temporary serializing insts renamed system.cpu.timesIdled 4 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ----------