# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# Authors: Lisa Hsu

# Configure the M5 cache hierarchy config in one place
#

import m5
from m5.objects import *
from Caches import *

def config_cache(options, system):
    if options.l2cache:
        system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
                            block_size=options.cacheline_size)
        system.tol2bus = Bus()
        system.l2.cpu_side = system.tol2bus.port
        system.l2.mem_side = system.membus.port
        system.l2.num_cpus = options.num_cpus

    for i in xrange(options.num_cpus):
        if options.caches:
            icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc,
                             block_size=options.cacheline_size)
            dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
                             block_size=options.cacheline_size)
            if buildEnv['TARGET_ISA'] == 'x86':
                system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
                                                      PageTableWalkerCache(),
                                                      PageTableWalkerCache())
            else:
                system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
        if options.l2cache:
            system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
        else:
            system.cpu[i].connectAllPorts(system.membus)

    return system