[root] type=Root children=system time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 [system] type=LinuxX86System children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus acpi_description_table_pointer=system.acpi_description_table_pointer boot_cpu_frequency=500 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table kernel=/arm/scratch/sysexplr/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem physmem=system.physmem readfile=tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt oem_id= revision=2 rsdt=Null xsdt=system.acpi_description_table_pointer.xsdt [system.acpi_description_table_pointer.xsdt] type=X86ACPIXSDT creator_id= creator_revision=0 entries= oem_id= oem_revision=0 oem_table_id= [system.bridge] type=Bridge delay=50000 filter_ranges_a=0:1152921504606846975 filter_ranges_b=0:134217727 nack_delay=4000 req_size_a=16 req_size_b=16 resp_size_a=16 resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[1] [system.cpu] type=DerivO3CPU children=dcache dtb dtb_walker_cache fuPool icache interrupts itb itb_walker_cache tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 cachePorts=200 checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 forwardComSize=5 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 phase=0 predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned smtIQThreshold=100 smtLSQPolicy=Partitioned smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 wbDepth=1 wbWidth=8 dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 forward_snoops=true hash_delay=1 is_top_level=true latency=1000 max_miss_count=0 mshrs=4 num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 subblock_size=0 tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.toL2Bus.port[2] [system.cpu.dtb] type=X86TLB children=walker size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker system=system port=system.cpu.dtb_walker_cache.cpu_side [system.cpu.dtb_walker_cache] type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true hash_delay=1 is_top_level=false latency=1000 max_miss_count=0 mshrs=10 num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 subblock_size=0 tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port mem_side=system.toL2Bus.port[4] [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc issueLat=1 opClass=IntAlu opLat=1 [system.cpu.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc issueLat=19 opClass=IntDiv opLat=20 [system.cpu.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=4 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc issueLat=1 opClass=FloatCvt opLat=2 [system.cpu.fuPool.FUList3] type=FUDesc children=opList0 opList1 opList2 count=2 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc issueLat=24 opClass=FloatSqrt opLat=24 [system.cpu.fuPool.FUList4] type=FUDesc children=opList count=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc issueLat=1 opClass=SimdFloatSqrt opLat=1 [system.cpu.fuPool.FUList6] type=FUDesc children=opList count=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 [system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 [system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess opLat=3 [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 forward_snoops=true hash_delay=1 is_top_level=true latency=1000 max_miss_count=0 mshrs=4 num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 subblock_size=0 tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.toL2Bus.port[1] [system.cpu.interrupts] type=X86LocalApic int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 platform=system.pc system=system int_port=system.membus.port[5] pio=system.membus.port[4] [system.cpu.itb] type=X86TLB children=walker size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker system=system port=system.cpu.itb_walker_cache.cpu_side [system.cpu.itb_walker_cache] type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true hash_delay=1 is_top_level=false latency=1000 max_miss_count=0 mshrs=10 num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 subblock_size=0 tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port mem_side=system.toL2Bus.port[3] [system.cpu.tracer] type=ExeTracer [system.e820_table] type=X86E820Table children=entries0 entries1 entries=system.e820_table.entries0 system.e820_table.entries1 [system.e820_table.entries0] type=X86E820Entry addr=0 range_type=2 size=1048576 [system.e820_table.entries1] type=X86E820Entry addr=1048576 range_type=1 size=133169152 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 imcr_present=true spec_rev=4 [system.intel_mp_table] type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= oem_table_addr=0 oem_table_size=0 product_id= spec_rev=4 [system.intel_mp_table.base_entries00] type=X86IntelMPProcessor bootstrap=true enable=true family=0 feature_flags=0 local_apic_id=0 local_apic_version=20 model=0 stepping=0 [system.intel_mp_table.base_entries01] type=X86IntelMPIOAPIC address=4273995776 enable=true id=1 version=17 [system.intel_mp_table.base_entries02] type=X86IntelMPBus bus_id=0 bus_type=ISA [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 bus_type=PCI [system.intel_mp_table.base_entries04] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=16 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 source_bus_irq=16 trigger=ConformTrigger [system.intel_mp_table.base_entries05] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=0 trigger=ConformTrigger [system.intel_mp_table.base_entries06] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=2 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=0 trigger=ConformTrigger [system.intel_mp_table.base_entries07] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=1 trigger=ConformTrigger [system.intel_mp_table.base_entries08] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=1 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=1 trigger=ConformTrigger [system.intel_mp_table.base_entries09] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=3 trigger=ConformTrigger [system.intel_mp_table.base_entries10] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=3 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=3 trigger=ConformTrigger [system.intel_mp_table.base_entries11] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=4 trigger=ConformTrigger [system.intel_mp_table.base_entries12] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=4 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=4 trigger=ConformTrigger [system.intel_mp_table.base_entries13] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=5 trigger=ConformTrigger [system.intel_mp_table.base_entries14] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=5 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=5 trigger=ConformTrigger [system.intel_mp_table.base_entries15] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=6 trigger=ConformTrigger [system.intel_mp_table.base_entries16] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=6 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=6 trigger=ConformTrigger [system.intel_mp_table.base_entries17] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=7 trigger=ConformTrigger [system.intel_mp_table.base_entries18] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=7 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=7 trigger=ConformTrigger [system.intel_mp_table.base_entries19] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=8 trigger=ConformTrigger [system.intel_mp_table.base_entries20] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=8 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=8 trigger=ConformTrigger [system.intel_mp_table.base_entries21] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=9 trigger=ConformTrigger [system.intel_mp_table.base_entries22] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=9 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=9 trigger=ConformTrigger [system.intel_mp_table.base_entries23] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=10 trigger=ConformTrigger [system.intel_mp_table.base_entries24] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=10 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=10 trigger=ConformTrigger [system.intel_mp_table.base_entries25] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=11 trigger=ConformTrigger [system.intel_mp_table.base_entries26] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=11 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=11 trigger=ConformTrigger [system.intel_mp_table.base_entries27] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=12 trigger=ConformTrigger [system.intel_mp_table.base_entries28] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=12 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=12 trigger=ConformTrigger [system.intel_mp_table.base_entries29] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=13 trigger=ConformTrigger [system.intel_mp_table.base_entries30] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=13 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=13 trigger=ConformTrigger [system.intel_mp_table.base_entries31] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 source_bus_irq=14 trigger=ConformTrigger [system.intel_mp_table.base_entries32] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=14 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 source_bus_irq=14 trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl sys=system [system.iobus] type=Bus block_size=64 bus_id=0 clock=1000 header_cycles=1 use_default_range=true width=64 default=system.pc.pciconfig.pio port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma [system.iocache] type=BaseCache addr_range=0:134217727 assoc=8 block_size=64 forward_snoops=false hash_delay=1 is_top_level=false latency=50000 max_miss_count=0 mshrs=20 num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 subblock_size=0 tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.port[18] mem_side=system.membus.port[2] [system.l2c] type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 forward_snoops=true hash_delay=1 is_top_level=false latency=10000 max_miss_count=0 mshrs=92 num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 subblock_size=0 tgts_per_mshr=16 trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.port[0] mem_side=system.membus.port[3] [system.membus] type=Bus children=badaddr_responder block_size=64 bus_id=1 clock=1000 header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.membus.badaddr_responder] type=IsaFake fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 platform=system.pc ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.membus.default [system.pc] type=Pc children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake fake_mem=false pio_addr=9223372036854779128 pio_latency=1000 pio_size=8 platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.iobus.port[12] [system.pc.com_1] type=Uart8250 children=terminal pio_addr=9223372036854776824 pio_latency=1000 platform=system.pc system=system terminal=system.pc.com_1.terminal pio=system.iobus.port[13] [system.pc.com_1.terminal] type=Terminal intr_control=system.intrctrl number=0 output=true port=3456 [system.pc.com_1.terminal] type=Terminal intr_control=system.intrctrl number=0 output=true port=3456 [system.pc.fake_com_2] type=IsaFake fake_mem=false pio_addr=9223372036854776568 pio_latency=1000 pio_size=8 platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.iobus.port[14] [system.pc.fake_com_3] type=IsaFake fake_mem=false pio_addr=9223372036854776808 pio_latency=1000 pio_size=8 platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.iobus.port[15] [system.pc.fake_com_4] type=IsaFake fake_mem=false pio_addr=9223372036854776552 pio_latency=1000 pio_size=8 platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.iobus.port[16] [system.pc.fake_floppy] type=IsaFake fake_mem=false pio_addr=9223372036854776818 pio_latency=1000 pio_size=2 platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.iobus.port[17] [system.pc.i_dont_exist] type=IsaFake fake_mem=false pio_addr=9223372036854775936 pio_latency=1000 pio_size=1 platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 ret_data64=18446744073709551615 ret_data8=255 system=system update_data=false warn_access= pio=system.iobus.port[11] [system.pc.pciconfig] type=PciConfigAll bus=0 pio_latency=1 platform=system.pc size=16777216 system=system pio=system.iobus.default [system.pc.south_bridge] type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 pic2=system.pc.south_bridge.pic2 pio_latency=1000 pit=system.pc.south_bridge.pit platform=system.pc speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos children=int_pin int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=1000 platform=system.pc system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.port[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin [system.pc.south_bridge.dma1] type=I8237 pio_addr=9223372036854775808 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[2] [system.pc.south_bridge.ide] type=IdeController children=disks0 disks1 BAR0=496 BAR0LegacyIO=true BAR0Size=8 BAR1=1012 BAR1LegacyIO=true BAR1Size=3 BAR2=368 BAR2LegacyIO=true BAR2Size=8 BAR3=884 BAR3LegacyIO=true BAR3Size=3 BAR4=1 BAR4LegacyIO=false BAR4Size=16 BAR5=1 BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 CardbusCIS=0 ClassCode=1 Command=0 DeviceID=28945 ExpansionROM=0 HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 MaximumLatency=0 MinimumGrant=0 ProgIF=128 Revision=0 Status=640 SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 io_shift=0 max_backoff_delay=10000000 min_backoff_delay=4000 pci_bus=0 pci_dev=4 pci_func=0 pio_latency=1000 platform=system.pc system=system config=system.iobus.port[19] dma=system.iobus.port[20] pio=system.iobus.port[3] [system.pc.south_bridge.ide.disks0] type=IdeDisk children=image delay=1000000 driveID=master image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage image_file=/arm/scratch/sysexplr/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] type=IdeDisk children=image delay=1000000 driveID=master image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 pio_latency=1000 platform=system.pc system=system int_port=system.iobus.port[10] pio=system.iobus.port[9] [system.pc.south_bridge.keyboard] type=I8042 children=keyboard_int_pin mouse_int_pin command_port=9223372036854775908 data_port=9223372036854775904 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[4] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin [system.pc.south_bridge.pic1] type=I8259 children=output mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 pio_latency=1000 platform=system.pc slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.port[5] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin [system.pc.south_bridge.pic2] type=I8259 children=output mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 pio_latency=1000 platform=system.pc slave=Null system=system pio=system.iobus.port[6] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin [system.pc.south_bridge.pit] type=I8254 children=int_pin int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[7] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin [system.pc.south_bridge.speaker] type=PcSpeaker i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[8] [system.physmem] type=PhysicalMemory file= latency=30000 latency_var=0 null=false range=0:134217727 zero=false port=system.membus.port[0] [system.smbios_table] type=X86SMBiosSMBiosTable children=structures major_version=2 minor_version=5 structures=system.smbios_table.structures [system.smbios_table.structures] type=X86SMBiosBiosInformation characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 major=0 minor=0 release_date=06/08/2008 rom_size=0 starting_addr_segment=0 vendor= version= [system.toL2Bus] type=Bus block_size=64 bus_id=0 clock=1000 header_cycles=1 use_default_range=false width=64 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side