================ Begin RubySystem Configuration Print ================ Ruby Configuration ------------------ protocol: MOSI_SMP_bcast compiled_at: 22:51:11, May 4 2009 RUBY_DEBUG: false hostname: piton g_RANDOM_SEED: 1 g_DEADLOCK_THRESHOLD: 500000 RANDOMIZATION: false g_SYNTHETIC_DRIVER: false g_DETERMINISTIC_DRIVER: false g_FILTERING_ENABLED: false g_DISTRIBUTED_PERSISTENT_ENABLED: true g_DYNAMIC_TIMEOUT_ENABLED: true g_RETRY_THRESHOLD: 1 g_FIXED_TIMEOUT_LATENCY: 300 g_trace_warmup_length: 1000000 g_bash_bandwidth_adaptive_threshold: 0.75 g_tester_length: 0 g_synthetic_locks: 2048 g_deterministic_addrs: 1 g_SpecifiedGenerator: DetermInvGenerator g_callback_counter: 0 g_NUM_COMPLETIONS_BEFORE_PASS: 0 g_NUM_SMT_THREADS: 1 g_think_time: 5 g_hold_time: 5 g_wait_time: 5 PROTOCOL_DEBUG_TRACE: true DEBUG_FILTER_STRING: none DEBUG_VERBOSITY_STRING: none DEBUG_START_TIME: 0 DEBUG_OUTPUT_FILENAME: none SIMICS_RUBY_MULTIPLIER: 4 OPAL_RUBY_MULTIPLIER: 1 TRANSACTION_TRACE_ENABLED: false USER_MODE_DATA_ONLY: false PROFILE_HOT_LINES: false PROFILE_ALL_INSTRUCTIONS: false PRINT_INSTRUCTION_TRACE: false g_DEBUG_CYCLE: 0 BLOCK_STC: false PERFECT_MEMORY_SYSTEM: false PERFECT_MEMORY_SYSTEM_LATENCY: 0 DATA_BLOCK: false REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false L1_CACHE_ASSOC: 4 L1_CACHE_NUM_SETS_BITS: 8 L2_CACHE_ASSOC: 4 L2_CACHE_NUM_SETS_BITS: 16 g_MEMORY_SIZE_BYTES: 4294967296 g_DATA_BLOCK_BYTES: 64 g_PAGE_SIZE_BYTES: 4096 g_REPLACEMENT_POLICY: PSEDUO_LRU g_NUM_PROCESSORS: 1 g_NUM_L2_BANKS: 1 g_NUM_MEMORIES: 1 g_PROCS_PER_CHIP: 1 g_NUM_CHIPS: 1 g_NUM_CHIP_BITS: 0 g_MEMORY_SIZE_BITS: 32 g_DATA_BLOCK_BITS: 6 g_PAGE_SIZE_BITS: 12 g_NUM_PROCESSORS_BITS: 0 g_PROCS_PER_CHIP_BITS: 0 g_NUM_L2_BANKS_BITS: 0 g_NUM_L2_BANKS_PER_CHIP_BITS: 0 g_NUM_L2_BANKS_PER_CHIP: 1 g_NUM_MEMORIES_BITS: 0 g_NUM_MEMORIES_PER_CHIP: 1 g_MEMORY_MODULE_BITS: 26 g_MEMORY_MODULE_BLOCKS: 67108864 MAP_L2BANKS_TO_LOWEST_BITS: false DIRECTORY_CACHE_LATENCY: 6 NULL_LATENCY: 1 ISSUE_LATENCY: 2 CACHE_RESPONSE_LATENCY: 12 L2_RESPONSE_LATENCY: 6 L2_TAG_LATENCY: 6 L1_RESPONSE_LATENCY: 3 MEMORY_RESPONSE_LATENCY_MINUS_2: 158 DIRECTORY_LATENCY: 80 NETWORK_LINK_LATENCY: 1 COPY_HEAD_LATENCY: 4 ON_CHIP_LINK_LATENCY: 1 RECYCLE_LATENCY: 10 L2_RECYCLE_LATENCY: 5 TIMER_LATENCY: 10000 TBE_RESPONSE_LATENCY: 1 PERIODIC_TIMER_WAKEUPS: true PROFILE_EXCEPTIONS: false PROFILE_XACT: true PROFILE_NONXACT: false XACT_DEBUG: true XACT_DEBUG_LEVEL: 1 XACT_MEMORY: false XACT_ENABLE_TOURMALINE: false XACT_NUM_CURRENT: 0 XACT_LAST_UPDATE: 0 XACT_ISOLATION_CHECK: false PERFECT_FILTER: true READ_WRITE_FILTER: Perfect_ PERFECT_VIRTUAL_FILTER: true VIRTUAL_READ_WRITE_FILTER: Perfect_ PERFECT_SUMMARY_FILTER: true SUMMARY_READ_WRITE_FILTER: Perfect_ XACT_EAGER_CD: true XACT_LAZY_VM: false XACT_CONFLICT_RES: BASE XACT_VISUALIZER: false XACT_COMMIT_TOKEN_LATENCY: 0 XACT_NO_BACKOFF: false XACT_LOG_BUFFER_SIZE: 0 XACT_STORE_PREDICTOR_HISTORY: 256 XACT_STORE_PREDICTOR_ENTRIES: 256 XACT_STORE_PREDICTOR_THRESHOLD: 4 XACT_FIRST_ACCESS_COST: 0 XACT_FIRST_PAGE_ACCESS_COST: 0 ENABLE_MAGIC_WAITING: false ENABLE_WATCHPOINT: false XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false ATMTP_ENABLED: false ATMTP_ABORT_ON_NON_XACT_INST: false ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false ATMTP_XACT_MAX_STORES: 32 ATMTP_DEBUG_LEVEL: 0 L1_REQUEST_LATENCY: 2 L2_REQUEST_LATENCY: 4 SINGLE_ACCESS_L2_BANKS: true SEQUENCER_TO_CONTROLLER_LATENCY: 4 L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32 L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32 DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32 g_SEQUENCER_OUTSTANDING_REQUESTS: 16 NUMBER_OF_TBES: 128 NUMBER_OF_L1_TBES: 32 NUMBER_OF_L2_TBES: 32 FINITE_BUFFERING: false FINITE_BUFFER_SIZE: 3 PROCESSOR_BUFFER_SIZE: 10 PROTOCOL_BUFFER_SIZE: 32 TSO: false g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH g_CACHE_DESIGN: NUCA g_endpoint_bandwidth: 10000 g_adaptive_routing: true NUMBER_OF_VIRTUAL_NETWORKS: 4 FAN_OUT_DEGREE: 4 g_PRINT_TOPOLOGY: true XACT_LENGTH: 0 XACT_SIZE: 0 ABORT_RETRY_TIME: 0 g_GARNET_NETWORK: false g_DETAIL_NETWORK: false g_NETWORK_TESTING: false g_FLIT_SIZE: 16 g_NUM_PIPE_STAGES: 4 g_VCS_PER_CLASS: 4 g_BUFFER_SIZE: 4 MEM_BUS_CYCLE_MULTIPLIER: 10 BANKS_PER_RANK: 8 RANKS_PER_DIMM: 2 DIMMS_PER_CHANNEL: 2 BANK_BIT_0: 8 RANK_BIT_0: 11 DIMM_BIT_0: 12 BANK_QUEUE_SIZE: 12 BANK_BUSY_TIME: 11 RANK_RANK_DELAY: 1 READ_WRITE_DELAY: 2 BASIC_BUS_BUSY_TIME: 2 MEM_CTL_LATENCY: 12 REFRESH_PERIOD: 1560 TFAW: 0 MEM_RANDOM_ARBITRATE: 0 MEM_FIXED_DELAY: 0 Chip Config ----------- Total_Chips: 1 L1Cache_TBEs numberPerChip: 1 TBEs_per_TBETable: 128 L1Cache_L1IcacheMemory numberPerChip: 1 Cache config: L1Cache_0_L1I cache_associativity: 4 num_cache_sets_bits: 8 num_cache_sets: 256 cache_set_size_bytes: 16384 cache_set_size_Kbytes: 16 cache_set_size_Mbytes: 0.015625 cache_size_bytes: 65536 cache_size_Kbytes: 64 cache_size_Mbytes: 0.0625 L1Cache_L1DcacheMemory numberPerChip: 1 Cache config: L1Cache_0_L1D cache_associativity: 4 num_cache_sets_bits: 8 num_cache_sets: 256 cache_set_size_bytes: 16384 cache_set_size_Kbytes: 16 cache_set_size_Mbytes: 0.015625 cache_size_bytes: 65536 cache_size_Kbytes: 64 cache_size_Mbytes: 0.0625 L1Cache_L2cacheMemory numberPerChip: 1 Cache config: L1Cache_0_L2 cache_associativity: 4 num_cache_sets_bits: 16 num_cache_sets: 65536 cache_set_size_bytes: 4194304 cache_set_size_Kbytes: 4096 cache_set_size_Mbytes: 4 cache_size_bytes: 16777216 cache_size_Kbytes: 16384 cache_size_Mbytes: 16 L1Cache_mandatoryQueue numberPerChip: 1 L1Cache_sequencer numberPerChip: 1 sequencer: Sequencer - SC max_outstanding_requests: 16 L1Cache_storeBuffer numberPerChip: 1 Store buffer entries: 128 (Only valid if TSO is enabled) Directory_directory numberPerChip: 1 Memory config: memory_bits: 32 memory_size_bytes: 4294967296 memory_size_Kbytes: 4.1943e+06 memory_size_Mbytes: 4096 memory_size_Gbytes: 4 module_bits: 26 module_size_lines: 67108864 module_size_bytes: 4294967296 module_size_Kbytes: 4.1943e+06 module_size_Mbytes: 4096 Network Configuration --------------------- network: SIMPLE_NETWORK topology: HIERARCHICAL_SWITCH virtual_net_0: active, ordered virtual_net_1: active, unordered virtual_net_2: inactive virtual_net_3: inactive --- Begin Topology Print --- Topology print ONLY indicates the _NETWORK_ latency between two machines It does NOT include the latency within the machines L1Cache-0 Network Latencies L1Cache-0 -> Directory-0 net_lat: 5 Directory-0 Network Latencies Directory-0 -> L1Cache-0 net_lat: 5 --- End Topology Print --- Profiler Configuration ---------------------- periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ Real time: May/05/2009 07:34:03 Profiler Stats -------------- Elapsed_time_in_seconds: 0 Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 Virtual_time_in_seconds: 0.27 Virtual_time_in_minutes: 0.0045 Virtual_time_in_hours: 7.5e-05 Virtual_time_in_days: 7.5e-05 Ruby_current_time: 9880001 Ruby_start_time: 1 Ruby_cycles: 9880000 mbytes_resident: 33.5469 mbytes_total: 194.562 resident_ratio: 0.172442 Total_misses: 256 total_misses: 256 [ 256 ] user_misses: 256 [ 256 ] supervisor_misses: 0 [ 0 ] instruction_executed: 1 [ 1 ] cycles_executed: 1 [ 1 ] cycles_per_instruction: 9.88e+06 [ 9.88e+06 ] misses_per_thousand_instructions: 256000 [ 256000 ] transactions_started: 0 [ 0 ] transactions_ended: 0 [ 0 ] instructions_per_transaction: 0 [ 0 ] cycles_per_transaction: 0 [ 0 ] misses_per_transaction: 0 [ 0 ] L1D_cache cache stats: L1D_cache_total_misses: 93 L1D_cache_total_demand_misses: 93 L1D_cache_total_prefetches: 0 L1D_cache_total_sw_prefetches: 0 L1D_cache_total_hw_prefetches: 0 L1D_cache_misses_per_transaction: 93 L1D_cache_misses_per_instruction: 93 L1D_cache_instructions_per_misses: 0.0107527 L1D_cache_request_type_LD: 59.1398% L1D_cache_request_type_ST: 40.8602% L1D_cache_access_mode_type_UserMode: 93 100% L1D_cache_request_size: [binsize: log2 max: 8 count: 93 average: 7.39785 | standard deviation: 1.44086 | 0 0 0 14 79 ] L1I_cache cache stats: L1I_cache_total_misses: 163 L1I_cache_total_demand_misses: 163 L1I_cache_total_prefetches: 0 L1I_cache_total_sw_prefetches: 0 L1I_cache_total_hw_prefetches: 0 L1I_cache_misses_per_transaction: 163 L1I_cache_misses_per_instruction: 163 L1I_cache_instructions_per_misses: 0.00613497 L1I_cache_request_type_IFETCH: 100% L1I_cache_access_mode_type_UserMode: 163 100% L1I_cache_request_size: [binsize: log2 max: 4 count: 163 average: 4 | standard deviation: 0 | 0 0 0 163 ] L2_cache cache stats: L2_cache_total_misses: 256 L2_cache_total_demand_misses: 256 L2_cache_total_prefetches: 0 L2_cache_total_sw_prefetches: 0 L2_cache_total_hw_prefetches: 0 L2_cache_misses_per_transaction: 256 L2_cache_misses_per_instruction: 256 L2_cache_instructions_per_misses: 0.00390625 L2_cache_request_type_LD: 21.4844% L2_cache_request_type_ST: 14.8438% L2_cache_request_type_IFETCH: 63.6719% L2_cache_access_mode_type_UserMode: 256 100% L2_cache_request_size: [binsize: log2 max: 8 count: 256 average: 5.23438 | standard deviation: 1.85134 | 0 0 0 177 79 ] Busy Controller Counts: L1Cache-0:0 Directory-0:0 Busy Bank Count:0 L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] L2TBE_usage: [binsize: 1 max: 0 count: 256 average: 0 | standard deviation: 0 | 256 ] StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] sequencer_requests_outstanding: [binsize: 1 max: 1 count: 256 average: 1 | standard deviation: 0 | 0 256 ] store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 1 max: 176 count: 256 average: 173.977 | standard deviation: 1.39185 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 58 56 44 51 ] miss_latency_LD: [binsize: 1 max: 176 count: 55 average: 173.945 | standard deviation: 1.36761 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 12 14 9 10 ] miss_latency_ST: [binsize: 1 max: 176 count: 38 average: 174.105 | standard deviation: 1.33558 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 9 8 9 7 ] miss_latency_IFETCH: [binsize: 1 max: 176 count: 163 average: 173.957 | standard deviation: 1.42075 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 37 34 26 34 ] miss_latency_NULL: [binsize: 1 max: 176 count: 256 average: 173.977 | standard deviation: 1.39185 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 58 56 44 51 ] miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] conflicting_histogram: [binsize: log2 max: 9843004 count: 256 average: 3.88873e+06 | standard deviation: 2.83442e+06 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 2 2 10 13 18 30 72 82 24 ] conflicting_histogram_percent: [binsize: log2 max: 9843004 count: 256 average: 3.88873e+06 | standard deviation: 2.83442e+06 | 0 0 0 0.390625 0 0 0 0 0 0 0 0 0 0 0.390625 0.390625 0.78125 0.78125 3.90625 5.07812 7.03125 11.7188 28.125 32.0312 9.375 ] Request vs. RubySystem State Profile -------------------------------- NP C GETS 55 21.4844 NP C GETX 27 10.5469 NP C GET_INSTR 163 63.6719 S S GETX 11 4.29688 filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Resource Usage -------------- page_size: 4096 user_time: 0 system_time: 0 page_reclaims: 8788 page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 64 MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:256 full:0 Network Stats ------------- switch_0_inlinks: 1 switch_0_outlinks: 1 links_utilized_percent_switch_0: 0.00207287 links_utilized_percent_switch_0_link_0: 0.00207287 bw: 10000 base_latency: 1 outgoing_messages_switch_0_link_0_Control: 256 2048 [ 256 0 0 0 ] base_latency: 1 switch_1_inlinks: 1 switch_1_outlinks: 1 links_utilized_percent_switch_1: 0.0186559 links_utilized_percent_switch_1_link_0: 0.0186559 bw: 10000 base_latency: 1 outgoing_messages_switch_1_link_0_Data: 256 18432 [ 0 256 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 links_utilized_percent_switch_2: 0.0114008 links_utilized_percent_switch_2_link_0: 0.0207287 bw: 10000 base_latency: 1 links_utilized_percent_switch_2_link_1: 0.00207287 bw: 10000 base_latency: 1 outgoing_messages_switch_2_link_0_Control: 256 2048 [ 256 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Data: 256 18432 [ 0 256 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Control: 256 2048 [ 256 0 0 0 ] base_latency: 1 Chip Stats ---------- --- L1Cache --- - Event Counts - Load 55 Ifetch 163 Store 38 L1_to_L2 0 L2_to_L1D 0 L2_to_L1I 0 L2_Replacement 0 Own_GETS 55 Own_GET_INSTR 163 Own_GETX 38 Own_PUTX 0 Other_GETS 0 Other_GET_INSTR 0 Other_GETX 0 Other_PUTX 0 Data 256 - Transitions - NP Load 55 NP Ifetch 163 NP Store 27 NP Other_GETS 0 <-- NP Other_GET_INSTR 0 <-- NP Other_GETX 0 <-- NP Other_PUTX 0 <-- I Load 0 <-- I Ifetch 0 <-- I Store 0 <-- I L1_to_L2 0 <-- I L2_to_L1D 0 <-- I L2_to_L1I 0 <-- I L2_Replacement 0 <-- I Other_GETS 0 <-- I Other_GET_INSTR 0 <-- I Other_GETX 0 <-- I Other_PUTX 0 <-- S Load 0 <-- S Ifetch 0 <-- S Store 11 S L1_to_L2 0 <-- S L2_to_L1D 0 <-- S L2_to_L1I 0 <-- S L2_Replacement 0 <-- S Other_GETS 0 <-- S Other_GET_INSTR 0 <-- S Other_GETX 0 <-- S Other_PUTX 0 <-- O Load 0 <-- O Ifetch 0 <-- O Store 0 <-- O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- O L2_Replacement 0 <-- O Other_GETS 0 <-- O Other_GET_INSTR 0 <-- O Other_GETX 0 <-- O Other_PUTX 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- M L1_to_L2 0 <-- M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- M L2_Replacement 0 <-- M Other_GETS 0 <-- M Other_GET_INSTR 0 <-- M Other_GETX 0 <-- M Other_PUTX 0 <-- IS_AD Load 0 <-- IS_AD Ifetch 0 <-- IS_AD Store 0 <-- IS_AD L1_to_L2 0 <-- IS_AD L2_to_L1D 0 <-- IS_AD L2_to_L1I 0 <-- IS_AD L2_Replacement 0 <-- IS_AD Own_GETS 55 IS_AD Own_GET_INSTR 163 IS_AD Other_GETS 0 <-- IS_AD Other_GET_INSTR 0 <-- IS_AD Other_GETX 0 <-- IS_AD Other_PUTX 0 <-- IS_AD Data 0 <-- IM_AD Load 0 <-- IM_AD Ifetch 0 <-- IM_AD Store 0 <-- IM_AD L1_to_L2 0 <-- IM_AD L2_to_L1D 0 <-- IM_AD L2_to_L1I 0 <-- IM_AD L2_Replacement 0 <-- IM_AD Own_GETX 27 IM_AD Other_GETS 0 <-- IM_AD Other_GET_INSTR 0 <-- IM_AD Other_GETX 0 <-- IM_AD Other_PUTX 0 <-- IM_AD Data 0 <-- SM_AD Load 0 <-- SM_AD Ifetch 0 <-- SM_AD Store 0 <-- SM_AD L1_to_L2 0 <-- SM_AD L2_to_L1D 0 <-- SM_AD L2_to_L1I 0 <-- SM_AD L2_Replacement 0 <-- SM_AD Own_GETX 11 SM_AD Other_GETS 0 <-- SM_AD Other_GET_INSTR 0 <-- SM_AD Other_GETX 0 <-- SM_AD Other_PUTX 0 <-- SM_AD Data 0 <-- OM_A Load 0 <-- OM_A Ifetch 0 <-- OM_A Store 0 <-- OM_A L1_to_L2 0 <-- OM_A L2_to_L1D 0 <-- OM_A L2_to_L1I 0 <-- OM_A L2_Replacement 0 <-- OM_A Own_GETX 0 <-- OM_A Other_GETS 0 <-- OM_A Other_GET_INSTR 0 <-- OM_A Other_GETX 0 <-- OM_A Other_PUTX 0 <-- OM_A Data 0 <-- IS_A Load 0 <-- IS_A Ifetch 0 <-- IS_A Store 0 <-- IS_A L1_to_L2 0 <-- IS_A L2_to_L1D 0 <-- IS_A L2_to_L1I 0 <-- IS_A L2_Replacement 0 <-- IS_A Own_GETS 0 <-- IS_A Own_GET_INSTR 0 <-- IS_A Other_GETS 0 <-- IS_A Other_GET_INSTR 0 <-- IS_A Other_GETX 0 <-- IS_A Other_PUTX 0 <-- IM_A Load 0 <-- IM_A Ifetch 0 <-- IM_A Store 0 <-- IM_A L1_to_L2 0 <-- IM_A L2_to_L1D 0 <-- IM_A L2_to_L1I 0 <-- IM_A L2_Replacement 0 <-- IM_A Own_GETX 0 <-- IM_A Other_GETS 0 <-- IM_A Other_GET_INSTR 0 <-- IM_A Other_GETX 0 <-- IM_A Other_PUTX 0 <-- SM_A Load 0 <-- SM_A Ifetch 0 <-- SM_A Store 0 <-- SM_A L1_to_L2 0 <-- SM_A L2_to_L1D 0 <-- SM_A L2_to_L1I 0 <-- SM_A L2_Replacement 0 <-- SM_A Own_GETX 0 <-- SM_A Other_GETS 0 <-- SM_A Other_GET_INSTR 0 <-- SM_A Other_GETX 0 <-- SM_A Other_PUTX 0 <-- MI_A Load 0 <-- MI_A Ifetch 0 <-- MI_A Store 0 <-- MI_A L1_to_L2 0 <-- MI_A L2_to_L1D 0 <-- MI_A L2_to_L1I 0 <-- MI_A L2_Replacement 0 <-- MI_A Own_PUTX 0 <-- MI_A Other_GETS 0 <-- MI_A Other_GET_INSTR 0 <-- MI_A Other_GETX 0 <-- MI_A Other_PUTX 0 <-- OI_A Load 0 <-- OI_A Ifetch 0 <-- OI_A Store 0 <-- OI_A L1_to_L2 0 <-- OI_A L2_to_L1D 0 <-- OI_A L2_to_L1I 0 <-- OI_A L2_Replacement 0 <-- OI_A Own_PUTX 0 <-- OI_A Other_GETS 0 <-- OI_A Other_GET_INSTR 0 <-- OI_A Other_GETX 0 <-- OI_A Other_PUTX 0 <-- II_A Load 0 <-- II_A Ifetch 0 <-- II_A Store 0 <-- II_A L1_to_L2 0 <-- II_A L2_to_L1D 0 <-- II_A L2_to_L1I 0 <-- II_A L2_Replacement 0 <-- II_A Own_PUTX 0 <-- II_A Other_GETS 0 <-- II_A Other_GET_INSTR 0 <-- II_A Other_GETX 0 <-- II_A Other_PUTX 0 <-- IS_D Load 0 <-- IS_D Ifetch 0 <-- IS_D Store 0 <-- IS_D L1_to_L2 0 <-- IS_D L2_to_L1D 0 <-- IS_D L2_to_L1I 0 <-- IS_D L2_Replacement 0 <-- IS_D Other_GETS 0 <-- IS_D Other_GET_INSTR 0 <-- IS_D Other_GETX 0 <-- IS_D Other_PUTX 0 <-- IS_D Data 218 IS_D_I Load 0 <-- IS_D_I Ifetch 0 <-- IS_D_I Store 0 <-- IS_D_I L1_to_L2 0 <-- IS_D_I L2_to_L1D 0 <-- IS_D_I L2_to_L1I 0 <-- IS_D_I L2_Replacement 0 <-- IS_D_I Other_GETS 0 <-- IS_D_I Other_GET_INSTR 0 <-- IS_D_I Other_GETX 0 <-- IS_D_I Other_PUTX 0 <-- IS_D_I Data 0 <-- IM_D Load 0 <-- IM_D Ifetch 0 <-- IM_D Store 0 <-- IM_D L1_to_L2 0 <-- IM_D L2_to_L1D 0 <-- IM_D L2_to_L1I 0 <-- IM_D L2_Replacement 0 <-- IM_D Other_GETS 0 <-- IM_D Other_GET_INSTR 0 <-- IM_D Other_GETX 0 <-- IM_D Other_PUTX 0 <-- IM_D Data 27 IM_D_O Load 0 <-- IM_D_O Ifetch 0 <-- IM_D_O Store 0 <-- IM_D_O L1_to_L2 0 <-- IM_D_O L2_to_L1D 0 <-- IM_D_O L2_to_L1I 0 <-- IM_D_O L2_Replacement 0 <-- IM_D_O Other_GETS 0 <-- IM_D_O Other_GET_INSTR 0 <-- IM_D_O Other_GETX 0 <-- IM_D_O Other_PUTX 0 <-- IM_D_O Data 0 <-- IM_D_I Load 0 <-- IM_D_I Ifetch 0 <-- IM_D_I Store 0 <-- IM_D_I L1_to_L2 0 <-- IM_D_I L2_to_L1D 0 <-- IM_D_I L2_to_L1I 0 <-- IM_D_I L2_Replacement 0 <-- IM_D_I Other_GETS 0 <-- IM_D_I Other_GET_INSTR 0 <-- IM_D_I Other_GETX 0 <-- IM_D_I Other_PUTX 0 <-- IM_D_I Data 0 <-- IM_D_OI Load 0 <-- IM_D_OI Ifetch 0 <-- IM_D_OI Store 0 <-- IM_D_OI L1_to_L2 0 <-- IM_D_OI L2_to_L1D 0 <-- IM_D_OI L2_to_L1I 0 <-- IM_D_OI L2_Replacement 0 <-- IM_D_OI Other_GETS 0 <-- IM_D_OI Other_GET_INSTR 0 <-- IM_D_OI Other_GETX 0 <-- IM_D_OI Other_PUTX 0 <-- IM_D_OI Data 0 <-- SM_D Load 0 <-- SM_D Ifetch 0 <-- SM_D Store 0 <-- SM_D L1_to_L2 0 <-- SM_D L2_to_L1D 0 <-- SM_D L2_to_L1I 0 <-- SM_D L2_Replacement 0 <-- SM_D Other_GETS 0 <-- SM_D Other_GET_INSTR 0 <-- SM_D Other_GETX 0 <-- SM_D Other_PUTX 0 <-- SM_D Data 11 SM_D_O Load 0 <-- SM_D_O Ifetch 0 <-- SM_D_O Store 0 <-- SM_D_O L1_to_L2 0 <-- SM_D_O L2_to_L1D 0 <-- SM_D_O L2_to_L1I 0 <-- SM_D_O L2_Replacement 0 <-- SM_D_O Other_GETS 0 <-- SM_D_O Other_GET_INSTR 0 <-- SM_D_O Other_GETX 0 <-- SM_D_O Other_PUTX 0 <-- SM_D_O Data 0 <-- --- Directory --- - Event Counts - OtherAddress 0 GETS 55 GET_INSTR 163 GETX 38 PUTX_Owner 0 PUTX_NotOwner 0 - Transitions - C OtherAddress 0 <-- C GETS 55 C GET_INSTR 163 C GETX 27 I GETS 0 <-- I GET_INSTR 0 <-- I GETX 0 <-- I PUTX_NotOwner 0 <-- S GETS 0 <-- S GET_INSTR 0 <-- S GETX 11 S PUTX_NotOwner 0 <-- SS GETS 0 <-- SS GET_INSTR 0 <-- SS GETX 0 <-- SS PUTX_NotOwner 0 <-- OS GETS 0 <-- OS GET_INSTR 0 <-- OS GETX 0 <-- OS PUTX_Owner 0 <-- OS PUTX_NotOwner 0 <-- OSS GETS 0 <-- OSS GET_INSTR 0 <-- OSS GETX 0 <-- OSS PUTX_Owner 0 <-- OSS PUTX_NotOwner 0 <-- M GETS 0 <-- M GET_INSTR 0 <-- M GETX 0 <-- M PUTX_Owner 0 <-- M PUTX_NotOwner 0 <--