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# Authors: Steve Reinhardt

import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
from Benchmarks import SysConfig
import FSConfig
from Caches import *

mem_size = '128MB'

#cpu
cpu = TimingSimpleCPU(cpu_id=0)
#the system
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')

system.cpu = cpu

#create the iocache
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave

#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
                              L1Cache(size = '32kB', assoc = 4),
                              L2Cache(size = '4MB', assoc = 8),
                              PageTableWalkerCache(),
                              PageTableWalkerCache())
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
cpu.connectAllPorts(system.membus)
# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'

root = Root(full_system=True, system=system)
m5.ticks.setGlobalFrequency('1THz')