================ Begin RubySystem Configuration Print ================ Ruby Configuration ------------------ protocol: MOSI_SMP_bcast compiled_at: 22:54:24, May 4 2009 RUBY_DEBUG: false hostname: piton g_RANDOM_SEED: 1 g_DEADLOCK_THRESHOLD: 500000 RANDOMIZATION: false g_SYNTHETIC_DRIVER: false g_DETERMINISTIC_DRIVER: false g_FILTERING_ENABLED: false g_DISTRIBUTED_PERSISTENT_ENABLED: true g_DYNAMIC_TIMEOUT_ENABLED: true g_RETRY_THRESHOLD: 1 g_FIXED_TIMEOUT_LATENCY: 300 g_trace_warmup_length: 1000000 g_bash_bandwidth_adaptive_threshold: 0.75 g_tester_length: 0 g_synthetic_locks: 2048 g_deterministic_addrs: 1 g_SpecifiedGenerator: DetermInvGenerator g_callback_counter: 0 g_NUM_COMPLETIONS_BEFORE_PASS: 0 g_NUM_SMT_THREADS: 1 g_think_time: 5 g_hold_time: 5 g_wait_time: 5 PROTOCOL_DEBUG_TRACE: true DEBUG_FILTER_STRING: none DEBUG_VERBOSITY_STRING: none DEBUG_START_TIME: 0 DEBUG_OUTPUT_FILENAME: none SIMICS_RUBY_MULTIPLIER: 4 OPAL_RUBY_MULTIPLIER: 1 TRANSACTION_TRACE_ENABLED: false USER_MODE_DATA_ONLY: false PROFILE_HOT_LINES: false PROFILE_ALL_INSTRUCTIONS: false PRINT_INSTRUCTION_TRACE: false g_DEBUG_CYCLE: 0 BLOCK_STC: false PERFECT_MEMORY_SYSTEM: false PERFECT_MEMORY_SYSTEM_LATENCY: 0 DATA_BLOCK: false REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false L1_CACHE_ASSOC: 4 L1_CACHE_NUM_SETS_BITS: 8 L2_CACHE_ASSOC: 4 L2_CACHE_NUM_SETS_BITS: 16 g_MEMORY_SIZE_BYTES: 4294967296 g_DATA_BLOCK_BYTES: 64 g_PAGE_SIZE_BYTES: 4096 g_REPLACEMENT_POLICY: PSEDUO_LRU g_NUM_PROCESSORS: 4 g_NUM_L2_BANKS: 4 g_NUM_MEMORIES: 4 g_PROCS_PER_CHIP: 1 g_NUM_CHIPS: 4 g_NUM_CHIP_BITS: 2 g_MEMORY_SIZE_BITS: 32 g_DATA_BLOCK_BITS: 6 g_PAGE_SIZE_BITS: 12 g_NUM_PROCESSORS_BITS: 2 g_PROCS_PER_CHIP_BITS: 0 g_NUM_L2_BANKS_BITS: 2 g_NUM_L2_BANKS_PER_CHIP_BITS: 0 g_NUM_L2_BANKS_PER_CHIP: 1 g_NUM_MEMORIES_BITS: 2 g_NUM_MEMORIES_PER_CHIP: 1 g_MEMORY_MODULE_BITS: 24 g_MEMORY_MODULE_BLOCKS: 16777216 MAP_L2BANKS_TO_LOWEST_BITS: false DIRECTORY_CACHE_LATENCY: 6 NULL_LATENCY: 1 ISSUE_LATENCY: 2 CACHE_RESPONSE_LATENCY: 12 L2_RESPONSE_LATENCY: 6 L2_TAG_LATENCY: 6 L1_RESPONSE_LATENCY: 3 MEMORY_RESPONSE_LATENCY_MINUS_2: 158 DIRECTORY_LATENCY: 80 NETWORK_LINK_LATENCY: 1 COPY_HEAD_LATENCY: 4 ON_CHIP_LINK_LATENCY: 1 RECYCLE_LATENCY: 10 L2_RECYCLE_LATENCY: 5 TIMER_LATENCY: 10000 TBE_RESPONSE_LATENCY: 1 PERIODIC_TIMER_WAKEUPS: true PROFILE_EXCEPTIONS: false PROFILE_XACT: true PROFILE_NONXACT: false XACT_DEBUG: true XACT_DEBUG_LEVEL: 1 XACT_MEMORY: false XACT_ENABLE_TOURMALINE: false XACT_NUM_CURRENT: 0 XACT_LAST_UPDATE: 0 XACT_ISOLATION_CHECK: false PERFECT_FILTER: true READ_WRITE_FILTER: Perfect_ PERFECT_VIRTUAL_FILTER: true VIRTUAL_READ_WRITE_FILTER: Perfect_ PERFECT_SUMMARY_FILTER: true SUMMARY_READ_WRITE_FILTER: Perfect_ XACT_EAGER_CD: true XACT_LAZY_VM: false XACT_CONFLICT_RES: BASE XACT_VISUALIZER: false XACT_COMMIT_TOKEN_LATENCY: 0 XACT_NO_BACKOFF: false XACT_LOG_BUFFER_SIZE: 0 XACT_STORE_PREDICTOR_HISTORY: 256 XACT_STORE_PREDICTOR_ENTRIES: 256 XACT_STORE_PREDICTOR_THRESHOLD: 4 XACT_FIRST_ACCESS_COST: 0 XACT_FIRST_PAGE_ACCESS_COST: 0 ENABLE_MAGIC_WAITING: false ENABLE_WATCHPOINT: false XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false ATMTP_ENABLED: false ATMTP_ABORT_ON_NON_XACT_INST: false ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false ATMTP_XACT_MAX_STORES: 32 ATMTP_DEBUG_LEVEL: 0 L1_REQUEST_LATENCY: 2 L2_REQUEST_LATENCY: 4 SINGLE_ACCESS_L2_BANKS: true SEQUENCER_TO_CONTROLLER_LATENCY: 4 L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32 L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32 DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32 g_SEQUENCER_OUTSTANDING_REQUESTS: 16 NUMBER_OF_TBES: 128 NUMBER_OF_L1_TBES: 32 NUMBER_OF_L2_TBES: 32 FINITE_BUFFERING: false FINITE_BUFFER_SIZE: 3 PROCESSOR_BUFFER_SIZE: 10 PROTOCOL_BUFFER_SIZE: 32 TSO: false g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH g_CACHE_DESIGN: NUCA g_endpoint_bandwidth: 10000 g_adaptive_routing: true NUMBER_OF_VIRTUAL_NETWORKS: 4 FAN_OUT_DEGREE: 4 g_PRINT_TOPOLOGY: true XACT_LENGTH: 0 XACT_SIZE: 0 ABORT_RETRY_TIME: 0 g_GARNET_NETWORK: false g_DETAIL_NETWORK: false g_NETWORK_TESTING: false g_FLIT_SIZE: 16 g_NUM_PIPE_STAGES: 4 g_VCS_PER_CLASS: 4 g_BUFFER_SIZE: 4 MEM_BUS_CYCLE_MULTIPLIER: 10 BANKS_PER_RANK: 8 RANKS_PER_DIMM: 2 DIMMS_PER_CHANNEL: 2 BANK_BIT_0: 8 RANK_BIT_0: 11 DIMM_BIT_0: 12 BANK_QUEUE_SIZE: 12 BANK_BUSY_TIME: 11 RANK_RANK_DELAY: 1 READ_WRITE_DELAY: 2 BASIC_BUS_BUSY_TIME: 2 MEM_CTL_LATENCY: 12 REFRESH_PERIOD: 1560 TFAW: 0 MEM_RANDOM_ARBITRATE: 0 MEM_FIXED_DELAY: 0 Chip Config ----------- Total_Chips: 4 L1Cache_TBEs numberPerChip: 1 TBEs_per_TBETable: 128 L1Cache_L1IcacheMemory numberPerChip: 1 Cache config: L1Cache_0_L1I cache_associativity: 4 num_cache_sets_bits: 8 num_cache_sets: 256 cache_set_size_bytes: 16384 cache_set_size_Kbytes: 16 cache_set_size_Mbytes: 0.015625 cache_size_bytes: 65536 cache_size_Kbytes: 64 cache_size_Mbytes: 0.0625 L1Cache_L1DcacheMemory numberPerChip: 1 Cache config: L1Cache_0_L1D cache_associativity: 4 num_cache_sets_bits: 8 num_cache_sets: 256 cache_set_size_bytes: 16384 cache_set_size_Kbytes: 16 cache_set_size_Mbytes: 0.015625 cache_size_bytes: 65536 cache_size_Kbytes: 64 cache_size_Mbytes: 0.0625 L1Cache_L2cacheMemory numberPerChip: 1 Cache config: L1Cache_0_L2 cache_associativity: 4 num_cache_sets_bits: 16 num_cache_sets: 65536 cache_set_size_bytes: 4194304 cache_set_size_Kbytes: 4096 cache_set_size_Mbytes: 4 cache_size_bytes: 16777216 cache_size_Kbytes: 16384 cache_size_Mbytes: 16 L1Cache_mandatoryQueue numberPerChip: 1 L1Cache_sequencer numberPerChip: 1 sequencer: Sequencer - SC max_outstanding_requests: 16 L1Cache_storeBuffer numberPerChip: 1 Store buffer entries: 128 (Only valid if TSO is enabled) Directory_directory numberPerChip: 1 Memory config: memory_bits: 32 memory_size_bytes: 4294967296 memory_size_Kbytes: 4.1943e+06 memory_size_Mbytes: 4096 memory_size_Gbytes: 4 module_bits: 24 module_size_lines: 16777216 module_size_bytes: 1073741824 module_size_Kbytes: 1.04858e+06 module_size_Mbytes: 1024 Network Configuration --------------------- network: SIMPLE_NETWORK topology: HIERARCHICAL_SWITCH virtual_net_0: active, ordered virtual_net_1: active, unordered virtual_net_2: inactive virtual_net_3: inactive --- Begin Topology Print --- Topology print ONLY indicates the _NETWORK_ latency between two machines It does NOT include the latency within the machines L1Cache-0 Network Latencies L1Cache-0 -> L1Cache-1 net_lat: 9 L1Cache-0 -> L1Cache-2 net_lat: 9 L1Cache-0 -> L1Cache-3 net_lat: 9 L1Cache-0 -> Directory-0 net_lat: 9 L1Cache-0 -> Directory-1 net_lat: 9 L1Cache-0 -> Directory-2 net_lat: 9 L1Cache-0 -> Directory-3 net_lat: 9 L1Cache-1 Network Latencies L1Cache-1 -> L1Cache-0 net_lat: 9 L1Cache-1 -> L1Cache-2 net_lat: 9 L1Cache-1 -> L1Cache-3 net_lat: 9 L1Cache-1 -> Directory-0 net_lat: 9 L1Cache-1 -> Directory-1 net_lat: 9 L1Cache-1 -> Directory-2 net_lat: 9 L1Cache-1 -> Directory-3 net_lat: 9 L1Cache-2 Network Latencies L1Cache-2 -> L1Cache-0 net_lat: 9 L1Cache-2 -> L1Cache-1 net_lat: 9 L1Cache-2 -> L1Cache-3 net_lat: 9 L1Cache-2 -> Directory-0 net_lat: 9 L1Cache-2 -> Directory-1 net_lat: 9 L1Cache-2 -> Directory-2 net_lat: 9 L1Cache-2 -> Directory-3 net_lat: 9 L1Cache-3 Network Latencies L1Cache-3 -> L1Cache-0 net_lat: 9 L1Cache-3 -> L1Cache-1 net_lat: 9 L1Cache-3 -> L1Cache-2 net_lat: 9 L1Cache-3 -> Directory-0 net_lat: 9 L1Cache-3 -> Directory-1 net_lat: 9 L1Cache-3 -> Directory-2 net_lat: 9 L1Cache-3 -> Directory-3 net_lat: 9 Directory-0 Network Latencies Directory-0 -> L1Cache-0 net_lat: 9 Directory-0 -> L1Cache-1 net_lat: 9 Directory-0 -> L1Cache-2 net_lat: 9 Directory-0 -> L1Cache-3 net_lat: 9 Directory-0 -> Directory-1 net_lat: 9 Directory-0 -> Directory-2 net_lat: 9 Directory-0 -> Directory-3 net_lat: 9 Directory-1 Network Latencies Directory-1 -> L1Cache-0 net_lat: 9 Directory-1 -> L1Cache-1 net_lat: 9 Directory-1 -> L1Cache-2 net_lat: 9 Directory-1 -> L1Cache-3 net_lat: 9 Directory-1 -> Directory-0 net_lat: 9 Directory-1 -> Directory-2 net_lat: 9 Directory-1 -> Directory-3 net_lat: 9 Directory-2 Network Latencies Directory-2 -> L1Cache-0 net_lat: 9 Directory-2 -> L1Cache-1 net_lat: 9 Directory-2 -> L1Cache-2 net_lat: 9 Directory-2 -> L1Cache-3 net_lat: 9 Directory-2 -> Directory-0 net_lat: 9 Directory-2 -> Directory-1 net_lat: 9 Directory-2 -> Directory-3 net_lat: 9 Directory-3 Network Latencies Directory-3 -> L1Cache-0 net_lat: 9 Directory-3 -> L1Cache-1 net_lat: 9 Directory-3 -> L1Cache-2 net_lat: 9 Directory-3 -> L1Cache-3 net_lat: 9 Directory-3 -> Directory-0 net_lat: 9 Directory-3 -> Directory-1 net_lat: 9 Directory-3 -> Directory-2 net_lat: 9 --- End Topology Print --- Profiler Configuration ---------------------- periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ Real time: May/05/2009 07:34:42 Profiler Stats -------------- Elapsed_time_in_seconds: 40 Elapsed_time_in_minutes: 0.666667 Elapsed_time_in_hours: 0.0111111 Elapsed_time_in_days: 0.000462963 Virtual_time_in_seconds: 37.33 Virtual_time_in_minutes: 0.622167 Virtual_time_in_hours: 0.0103694 Virtual_time_in_days: 0.0103694 Ruby_current_time: 2480212001 Ruby_start_time: 1 Ruby_cycles: 2480212000 mbytes_resident: 90.6484 mbytes_total: 252.043 resident_ratio: 0.35967 Total_misses: 1949 total_misses: 1949 [ 424 409 702 414 ] user_misses: 1949 [ 424 409 702 414 ] supervisor_misses: 0 [ 0 0 0 0 ] instruction_executed: 4 [ 1 1 1 1 ] cycles_executed: 4 [ 1 1 1 1 ] cycles_per_instruction: 2.48021e+09 [ 2.48021e+09 2.48021e+09 2.48021e+09 2.48021e+09 ] misses_per_thousand_instructions: 487250 [ 424000 409000 702000 414000 ] transactions_started: 0 [ 0 0 0 0 ] transactions_ended: 0 [ 0 0 0 0 ] instructions_per_transaction: 0 [ 0 0 0 0 ] cycles_per_transaction: 0 [ 0 0 0 0 ] misses_per_transaction: 0 [ 0 0 0 0 ] L1D_cache cache stats: L1D_cache_total_misses: 1340 L1D_cache_total_demand_misses: 1340 L1D_cache_total_prefetches: 0 L1D_cache_total_sw_prefetches: 0 L1D_cache_total_hw_prefetches: 0 L1D_cache_misses_per_transaction: 1340 L1D_cache_misses_per_instruction: 1340 L1D_cache_instructions_per_misses: 0.000746269 L1D_cache_request_type_LD: 47.4627% L1D_cache_request_type_ST: 38.0597% L1D_cache_request_type_ATOMIC: 14.4776% L1D_cache_access_mode_type_UserMode: 1340 100% L1D_cache_request_size: [binsize: log2 max: 8 count: 1340 average: 3.48881 | standard deviation: 2.44812 | 0 527 4 583 226 ] L1I_cache cache stats: L1I_cache_total_misses: 610 L1I_cache_total_demand_misses: 610 L1I_cache_total_prefetches: 0 L1I_cache_total_sw_prefetches: 0 L1I_cache_total_hw_prefetches: 0 L1I_cache_misses_per_transaction: 610 L1I_cache_misses_per_instruction: 610 L1I_cache_instructions_per_misses: 0.00163934 L1I_cache_request_type_IFETCH: 100% L1I_cache_access_mode_type_UserMode: 610 100% L1I_cache_request_size: [binsize: log2 max: 4 count: 610 average: 4 | standard deviation: 0 | 0 0 0 610 ] L2_cache cache stats: L2_cache_total_misses: 1949 L2_cache_total_demand_misses: 1949 L2_cache_total_prefetches: 0 L2_cache_total_sw_prefetches: 0 L2_cache_total_hw_prefetches: 0 L2_cache_misses_per_transaction: 1949 L2_cache_misses_per_instruction: 1949 L2_cache_instructions_per_misses: 0.000513084 L2_cache_request_type_LD: 32.6321% L2_cache_request_type_ST: 26.1673% L2_cache_request_type_ATOMIC: 9.95382% L2_cache_request_type_IFETCH: 31.2468% L2_cache_access_mode_type_UserMode: 1949 100% L2_cache_request_size: [binsize: log2 max: 8 count: 1949 average: 3.64854 | standard deviation: 2.04355 | 0 527 4 1192 226 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 Directory-0:0 Directory-1:0 Directory-2:0 Directory-3:0 Busy Bank Count:0 L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] L2TBE_usage: [binsize: 1 max: 0 count: 1949 average: 0 | standard deviation: 0 | 1949 ] StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] sequencer_requests_outstanding: [binsize: 1 max: 1 count: 1950 average: 1 | standard deviation: 0 | 0 1950 ] store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ] miss_latency_LD: [binsize: 1 max: 184 count: 636 average: 57.2925 | standard deviation: 53.9711 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 536 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 19 26 17 23 ] miss_latency_ST: [binsize: 1 max: 184 count: 510 average: 73.749 | standard deviation: 69.6824 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34 27 26 19 42 ] miss_latency_ATOMIC: [binsize: 1 max: 183 count: 194 average: 37.7887 | standard deviation: 23.3543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 0 1 ] miss_latency_IFETCH: [binsize: 1 max: 184 count: 610 average: 181.728 | standard deviation: 7.34165 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 113 125 131 117 123 ] miss_latency_NULL: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ] miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] conflicting_histogram: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 6 7 6 10 37 57 33 164 243 38 123 210 142 218 449 203 ] conflicting_histogram_percent: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 0.0513084 0 0 0 0 0 0 0 0 0 0 0.0513084 0 0.0513084 0.30785 0.359159 0.30785 0.513084 1.89841 2.92458 1.69318 8.41457 12.4679 1.94972 6.31093 10.7748 7.28579 11.1852 23.0375 10.4156 ] Request vs. RubySystem State Profile -------------------------------- I M GETS 310 15.9056 I M GETX 216 11.0826 I OS GETS 142 7.28579 I OS GETX 33 1.69318 I OSS GETS 54 2.77065 I OSS GETX 15 0.769625 NP C GETS 75 3.84813 NP C GETX 136 6.97794 NP C GET_INSTR 348 17.8553 NP M GETS 17 0.872242 NP M GETX 11 0.564392 NP OS GETS 6 0.30785 NP OSS GETS 7 0.359159 NP S GETS 9 0.461775 NP S GET_INSTR 93 4.77168 NP SS GETS 16 0.820934 NP SS GET_INSTR 168 8.61981 O OS GETX 22 1.12878 O OSS GETX 60 3.0785 S OS GETX 124 6.36224 S OSS GETX 70 3.59159 S S GETX 17 0.872242 filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Resource Usage -------------- page_size: 4096 user_time: 37 system_time: 0 page_reclaims: 23404 page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 656 MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:424 full:0 MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:409 full:0 MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:703 full:0 MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:414 full:0 Network Stats ------------- switch_0_inlinks: 1 switch_0_outlinks: 1 links_utilized_percent_switch_0: 8.82828e-05 links_utilized_percent_switch_0_link_0: 8.82828e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_0_link_0_Control: 424 3392 [ 424 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Data: 257 18504 [ 0 257 0 0 ] base_latency: 1 switch_1_inlinks: 1 switch_1_outlinks: 1 links_utilized_percent_switch_1: 8.92504e-05 links_utilized_percent_switch_1_link_0: 8.92504e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_1_link_0_Control: 409 3272 [ 409 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Data: 262 18864 [ 0 262 0 0 ] base_latency: 1 switch_2_inlinks: 1 switch_2_outlinks: 1 links_utilized_percent_switch_2: 8.94117e-05 links_utilized_percent_switch_2_link_0: 8.94117e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_2_link_0_Control: 702 5616 [ 702 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Data: 230 16560 [ 0 230 0 0 ] base_latency: 1 switch_3_inlinks: 1 switch_3_outlinks: 1 links_utilized_percent_switch_3: 8.76699e-05 links_utilized_percent_switch_3_link_0: 8.76699e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_3_link_0_Control: 414 3312 [ 414 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Data: 256 18432 [ 0 256 0 0 ] base_latency: 1 switch_4_inlinks: 1 switch_4_outlinks: 1 links_utilized_percent_switch_4: 6.76394e-05 links_utilized_percent_switch_4_link_0: 6.76394e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_4_link_0_Data: 233 16776 [ 0 233 0 0 ] base_latency: 1 switch_5_inlinks: 1 switch_5_outlinks: 1 links_utilized_percent_switch_5: 6.21237e-05 links_utilized_percent_switch_5_link_0: 6.21237e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_5_link_0_Data: 214 15408 [ 0 214 0 0 ] base_latency: 1 switch_6_inlinks: 1 switch_6_outlinks: 1 links_utilized_percent_switch_6: 5.9511e-05 links_utilized_percent_switch_6_link_0: 5.9511e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_6_link_0_Data: 205 14760 [ 0 205 0 0 ] base_latency: 1 switch_7_inlinks: 1 switch_7_outlinks: 1 links_utilized_percent_switch_7: 6.09625e-05 links_utilized_percent_switch_7_link_0: 6.09625e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_7_link_0_Data: 210 15120 [ 0 210 0 0 ] base_latency: 1 switch_8_inlinks: 4 switch_8_outlinks: 1 links_utilized_percent_switch_8: 0.000354615 links_utilized_percent_switch_8_link_0: 0.000354615 bw: 10000 base_latency: 1 outgoing_messages_switch_8_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_0_Data: 1005 72360 [ 0 1005 0 0 ] base_latency: 1 switch_9_inlinks: 4 switch_9_outlinks: 1 links_utilized_percent_switch_9: 0.000250237 links_utilized_percent_switch_9_link_0: 0.000250237 bw: 10000 base_latency: 1 outgoing_messages_switch_9_link_0_Data: 862 62064 [ 0 862 0 0 ] base_latency: 1 switch_10_inlinks: 2 switch_10_outlinks: 2 links_utilized_percent_switch_10: 0.000333859 links_utilized_percent_switch_10_link_0: 0.000604852 bw: 10000 base_latency: 1 links_utilized_percent_switch_10_link_1: 6.28656e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_10_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_0_Data: 1867 134424 [ 0 1867 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 switch_11_inlinks: 1 switch_11_outlinks: 4 links_utilized_percent_switch_11: 0.000198362 links_utilized_percent_switch_11_link_0: 0.000181597 bw: 10000 base_latency: 1 links_utilized_percent_switch_11_link_1: 0.000176082 bw: 10000 base_latency: 1 links_utilized_percent_switch_11_link_2: 0.000257655 bw: 10000 base_latency: 1 links_utilized_percent_switch_11_link_3: 0.000178114 bw: 10000 base_latency: 1 outgoing_messages_switch_11_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 outgoing_messages_switch_11_link_0_Data: 409 29448 [ 0 409 0 0 ] base_latency: 1 outgoing_messages_switch_11_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 outgoing_messages_switch_11_link_1_Data: 390 28080 [ 0 390 0 0 ] base_latency: 1 outgoing_messages_switch_11_link_2_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 outgoing_messages_switch_11_link_2_Data: 671 48312 [ 0 671 0 0 ] base_latency: 1 outgoing_messages_switch_11_link_3_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 outgoing_messages_switch_11_link_3_Data: 397 28584 [ 0 397 0 0 ] base_latency: 1 switch_12_inlinks: 1 switch_12_outlinks: 4 links_utilized_percent_switch_12: 1.57164e-05 links_utilized_percent_switch_12_link_0: 2.37399e-05 bw: 10000 base_latency: 1 links_utilized_percent_switch_12_link_1: 1.05475e-05 bw: 10000 base_latency: 1 links_utilized_percent_switch_12_link_2: 6.87038e-06 bw: 10000 base_latency: 1 links_utilized_percent_switch_12_link_3: 2.17078e-05 bw: 10000 base_latency: 1 outgoing_messages_switch_12_link_0_Control: 736 5888 [ 736 0 0 0 ] base_latency: 1 outgoing_messages_switch_12_link_1_Control: 327 2616 [ 327 0 0 0 ] base_latency: 1 outgoing_messages_switch_12_link_2_Control: 213 1704 [ 213 0 0 0 ] base_latency: 1 outgoing_messages_switch_12_link_3_Control: 673 5384 [ 673 0 0 0 ] base_latency: 1 Chip Stats ---------- --- L1Cache --- - Event Counts - Load 636 Ifetch 610 Store 704 L1_to_L2 3 L2_to_L1D 0 L2_to_L1I 1 L2_Replacement 0 Own_GETS 636 Own_GET_INSTR 609 Own_GETX 704 Own_PUTX 0 Other_GETS 1908 Other_GET_INSTR 1827 Other_GETX 2112 Other_PUTX 0 Data 1867 - Transitions - NP Load 130 NP Ifetch 609 NP Store 147 NP Other_GETS 289 NP Other_GET_INSTR 1323 NP Other_GETX 514 NP Other_PUTX 0 <-- I Load 506 I Ifetch 0 <-- I Store 264 I L1_to_L2 0 <-- I L2_to_L1D 0 <-- I L2_to_L1I 0 <-- I L2_Replacement 0 <-- I Other_GETS 765 I Other_GET_INSTR 0 <-- I Other_GETX 796 I Other_PUTX 0 <-- S Load 0 <-- S Ifetch 1 S Store 211 S L1_to_L2 2 S L2_to_L1D 0 <-- S L2_to_L1I 1 S L2_Replacement 0 <-- S Other_GETS 318 S Other_GET_INSTR 504 S Other_GETX 333 S Other_PUTX 0 <-- O Load 0 <-- O Ifetch 0 <-- O Store 82 O L1_to_L2 0 <-- O L2_to_L1D 0 <-- O L2_to_L1I 0 <-- O L2_Replacement 0 <-- O Other_GETS 209 O Other_GET_INSTR 0 <-- O Other_GETX 242 O Other_PUTX 0 <-- M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- M L1_to_L2 1 M L2_to_L1D 0 <-- M L2_to_L1I 0 <-- M L2_Replacement 0 <-- M Other_GETS 327 M Other_GET_INSTR 0 <-- M Other_GETX 227 M Other_PUTX 0 <-- IS_AD Load 0 <-- IS_AD Ifetch 0 <-- IS_AD Store 0 <-- IS_AD L1_to_L2 0 <-- IS_AD L2_to_L1D 0 <-- IS_AD L2_to_L1I 0 <-- IS_AD L2_Replacement 0 <-- IS_AD Own_GETS 636 IS_AD Own_GET_INSTR 609 IS_AD Other_GETS 0 <-- IS_AD Other_GET_INSTR 0 <-- IS_AD Other_GETX 0 <-- IS_AD Other_PUTX 0 <-- IS_AD Data 0 <-- IM_AD Load 0 <-- IM_AD Ifetch 0 <-- IM_AD Store 0 <-- IM_AD L1_to_L2 0 <-- IM_AD L2_to_L1D 0 <-- IM_AD L2_to_L1I 0 <-- IM_AD L2_Replacement 0 <-- IM_AD Own_GETX 411 IM_AD Other_GETS 0 <-- IM_AD Other_GET_INSTR 0 <-- IM_AD Other_GETX 0 <-- IM_AD Other_PUTX 0 <-- IM_AD Data 0 <-- SM_AD Load 0 <-- SM_AD Ifetch 0 <-- SM_AD Store 0 <-- SM_AD L1_to_L2 0 <-- SM_AD L2_to_L1D 0 <-- SM_AD L2_to_L1I 0 <-- SM_AD L2_Replacement 0 <-- SM_AD Own_GETX 211 SM_AD Other_GETS 0 <-- SM_AD Other_GET_INSTR 0 <-- SM_AD Other_GETX 0 <-- SM_AD Other_PUTX 0 <-- SM_AD Data 0 <-- OM_A Load 0 <-- OM_A Ifetch 0 <-- OM_A Store 0 <-- OM_A L1_to_L2 0 <-- OM_A L2_to_L1D 0 <-- OM_A L2_to_L1I 0 <-- OM_A L2_Replacement 0 <-- OM_A Own_GETX 82 OM_A Other_GETS 0 <-- OM_A Other_GET_INSTR 0 <-- OM_A Other_GETX 0 <-- OM_A Other_PUTX 0 <-- OM_A Data 0 <-- IS_A Load 0 <-- IS_A Ifetch 0 <-- IS_A Store 0 <-- IS_A L1_to_L2 0 <-- IS_A L2_to_L1D 0 <-- IS_A L2_to_L1I 0 <-- IS_A L2_Replacement 0 <-- IS_A Own_GETS 0 <-- IS_A Own_GET_INSTR 0 <-- IS_A Other_GETS 0 <-- IS_A Other_GET_INSTR 0 <-- IS_A Other_GETX 0 <-- IS_A Other_PUTX 0 <-- IM_A Load 0 <-- IM_A Ifetch 0 <-- IM_A Store 0 <-- IM_A L1_to_L2 0 <-- IM_A L2_to_L1D 0 <-- IM_A L2_to_L1I 0 <-- IM_A L2_Replacement 0 <-- IM_A Own_GETX 0 <-- IM_A Other_GETS 0 <-- IM_A Other_GET_INSTR 0 <-- IM_A Other_GETX 0 <-- IM_A Other_PUTX 0 <-- SM_A Load 0 <-- SM_A Ifetch 0 <-- SM_A Store 0 <-- SM_A L1_to_L2 0 <-- SM_A L2_to_L1D 0 <-- SM_A L2_to_L1I 0 <-- SM_A L2_Replacement 0 <-- SM_A Own_GETX 0 <-- SM_A Other_GETS 0 <-- SM_A Other_GET_INSTR 0 <-- SM_A Other_GETX 0 <-- SM_A Other_PUTX 0 <-- MI_A Load 0 <-- MI_A Ifetch 0 <-- MI_A Store 0 <-- MI_A L1_to_L2 0 <-- MI_A L2_to_L1D 0 <-- MI_A L2_to_L1I 0 <-- MI_A L2_Replacement 0 <-- MI_A Own_PUTX 0 <-- MI_A Other_GETS 0 <-- MI_A Other_GET_INSTR 0 <-- MI_A Other_GETX 0 <-- MI_A Other_PUTX 0 <-- OI_A Load 0 <-- OI_A Ifetch 0 <-- OI_A Store 0 <-- OI_A L1_to_L2 0 <-- OI_A L2_to_L1D 0 <-- OI_A L2_to_L1I 0 <-- OI_A L2_Replacement 0 <-- OI_A Own_PUTX 0 <-- OI_A Other_GETS 0 <-- OI_A Other_GET_INSTR 0 <-- OI_A Other_GETX 0 <-- OI_A Other_PUTX 0 <-- II_A Load 0 <-- II_A Ifetch 0 <-- II_A Store 0 <-- II_A L1_to_L2 0 <-- II_A L2_to_L1D 0 <-- II_A L2_to_L1I 0 <-- II_A L2_Replacement 0 <-- II_A Own_PUTX 0 <-- II_A Other_GETS 0 <-- II_A Other_GET_INSTR 0 <-- II_A Other_GETX 0 <-- II_A Other_PUTX 0 <-- IS_D Load 0 <-- IS_D Ifetch 0 <-- IS_D Store 0 <-- IS_D L1_to_L2 0 <-- IS_D L2_to_L1D 0 <-- IS_D L2_to_L1I 0 <-- IS_D L2_Replacement 0 <-- IS_D Other_GETS 0 <-- IS_D Other_GET_INSTR 0 <-- IS_D Other_GETX 0 <-- IS_D Other_PUTX 0 <-- IS_D Data 1245 IS_D_I Load 0 <-- IS_D_I Ifetch 0 <-- IS_D_I Store 0 <-- IS_D_I L1_to_L2 0 <-- IS_D_I L2_to_L1D 0 <-- IS_D_I L2_to_L1I 0 <-- IS_D_I L2_Replacement 0 <-- IS_D_I Other_GETS 0 <-- IS_D_I Other_GET_INSTR 0 <-- IS_D_I Other_GETX 0 <-- IS_D_I Other_PUTX 0 <-- IS_D_I Data 0 <-- IM_D Load 0 <-- IM_D Ifetch 0 <-- IM_D Store 0 <-- IM_D L1_to_L2 0 <-- IM_D L2_to_L1D 0 <-- IM_D L2_to_L1I 0 <-- IM_D L2_Replacement 0 <-- IM_D Other_GETS 0 <-- IM_D Other_GET_INSTR 0 <-- IM_D Other_GETX 0 <-- IM_D Other_PUTX 0 <-- IM_D Data 411 IM_D_O Load 0 <-- IM_D_O Ifetch 0 <-- IM_D_O Store 0 <-- IM_D_O L1_to_L2 0 <-- IM_D_O L2_to_L1D 0 <-- IM_D_O L2_to_L1I 0 <-- IM_D_O L2_Replacement 0 <-- IM_D_O Other_GETS 0 <-- IM_D_O Other_GET_INSTR 0 <-- IM_D_O Other_GETX 0 <-- IM_D_O Other_PUTX 0 <-- IM_D_O Data 0 <-- IM_D_I Load 0 <-- IM_D_I Ifetch 0 <-- IM_D_I Store 0 <-- IM_D_I L1_to_L2 0 <-- IM_D_I L2_to_L1D 0 <-- IM_D_I L2_to_L1I 0 <-- IM_D_I L2_Replacement 0 <-- IM_D_I Other_GETS 0 <-- IM_D_I Other_GET_INSTR 0 <-- IM_D_I Other_GETX 0 <-- IM_D_I Other_PUTX 0 <-- IM_D_I Data 0 <-- IM_D_OI Load 0 <-- IM_D_OI Ifetch 0 <-- IM_D_OI Store 0 <-- IM_D_OI L1_to_L2 0 <-- IM_D_OI L2_to_L1D 0 <-- IM_D_OI L2_to_L1I 0 <-- IM_D_OI L2_Replacement 0 <-- IM_D_OI Other_GETS 0 <-- IM_D_OI Other_GET_INSTR 0 <-- IM_D_OI Other_GETX 0 <-- IM_D_OI Other_PUTX 0 <-- IM_D_OI Data 0 <-- SM_D Load 0 <-- SM_D Ifetch 0 <-- SM_D Store 0 <-- SM_D L1_to_L2 0 <-- SM_D L2_to_L1D 0 <-- SM_D L2_to_L1I 0 <-- SM_D L2_Replacement 0 <-- SM_D Other_GETS 0 <-- SM_D Other_GET_INSTR 0 <-- SM_D Other_GETX 0 <-- SM_D Other_PUTX 0 <-- SM_D Data 211 SM_D_O Load 0 <-- SM_D_O Ifetch 0 <-- SM_D_O Store 0 <-- SM_D_O L1_to_L2 0 <-- SM_D_O L2_to_L1D 0 <-- SM_D_O L2_to_L1I 0 <-- SM_D_O L2_Replacement 0 <-- SM_D_O Other_GETS 0 <-- SM_D_O Other_GET_INSTR 0 <-- SM_D_O Other_GETX 0 <-- SM_D_O Other_PUTX 0 <-- SM_D_O Data 0 <-- --- Directory --- - Event Counts - OtherAddress 0 GETS 636 GET_INSTR 609 GETX 704 PUTX_Owner 0 PUTX_NotOwner 0 - Transitions - C OtherAddress 0 <-- C GETS 75 C GET_INSTR 348 C GETX 136 I GETS 0 <-- I GET_INSTR 0 <-- I GETX 0 <-- I PUTX_NotOwner 0 <-- S GETS 9 S GET_INSTR 93 S GETX 17 S PUTX_NotOwner 0 <-- SS GETS 16 SS GET_INSTR 168 SS GETX 0 <-- SS PUTX_NotOwner 0 <-- OS GETS 148 OS GET_INSTR 0 <-- OS GETX 179 OS PUTX_Owner 0 <-- OS PUTX_NotOwner 0 <-- OSS GETS 61 OSS GET_INSTR 0 <-- OSS GETX 145 OSS PUTX_Owner 0 <-- OSS PUTX_NotOwner 0 <-- M GETS 327 M GET_INSTR 0 <-- M GETX 227 M PUTX_Owner 0 <-- M PUTX_NotOwner 0 <--