================ Begin RubySystem Configuration Print ================ RubySystem config: random_seed: 184716 randomization: 0 tech_nm: 45 freq_mhz: 3000 block_size_bytes: 64 block_size_bits: 6 memory_size_bytes: 1073741824 memory_size_bits: 30 DMA_Controller config: DMAController_0 version: 0 buffer_size: 32 dma_sequencer: DMASequencer_0 number_of_TBEs: 128 transitions_per_cycle: 32 Directory_Controller config: DirectoryController_0 version: 0 buffer_size: 32 directory_latency: 6 directory_name: DirectoryMemory_0 memory_controller_name: MemoryControl_0 memory_latency: 158 number_of_TBEs: 128 recycle_latency: 10 to_mem_ctrl_latency: 1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_0 version: 0 buffer_size: 32 cache: l1u_0 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 128 sequencer: Sequencer_0 transitions_per_cycle: 32 Cache config: l1u_0 controller: L1CacheController_0 cache_associativity: 8 num_cache_sets_bits: 2 num_cache_sets: 4 cache_set_size_bytes: 256 cache_set_size_Kbytes: 0.25 cache_set_size_Mbytes: 0.000244141 cache_size_bytes: 2048 cache_size_Kbytes: 2 cache_size_Mbytes: 0.00195312 DirectoryMemory Global Config: number of directory memories: 1 total memory size bytes: 1073741824 total memory size bits: 30 DirectoryMemory module config: DirectoryMemory_0 controller: DirectoryController_0 version: 0 memory_bits: 30 memory_size_bytes: 1073741824 memory_size_Kbytes: 1.04858e+06 memory_size_Mbytes: 1024 memory_size_Gbytes: 1 Seqeuncer config: Sequencer_0 controller: L1CacheController_0 version: 0 max_outstanding_requests: 16 deadlock_threshold: 500000 Network Configuration --------------------- network: SIMPLE_NETWORK topology: theTopology virtual_net_0: active, ordered virtual_net_1: active, ordered virtual_net_2: active, ordered virtual_net_3: inactive virtual_net_4: active, ordered virtual_net_5: active, ordered --- Begin Topology Print --- Topology print ONLY indicates the _NETWORK_ latency between two machines It does NOT include the latency within the machines L1Cache-0 Network Latencies L1Cache-0 -> Directory-0 net_lat: 7 L1Cache-0 -> DMA-0 net_lat: 7 Directory-0 Network Latencies Directory-0 -> L1Cache-0 net_lat: 7 Directory-0 -> DMA-0 net_lat: 7 DMA-0 Network Latencies DMA-0 -> L1Cache-0 net_lat: 7 DMA-0 -> Directory-0 net_lat: 7 --- End Topology Print --- Profiler Configuration ---------------------- periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ Real time: Jul/06/2009 11:11:44 Profiler Stats -------------- Elapsed_time_in_seconds: 1 Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 Virtual_time_in_seconds: 0.87 Virtual_time_in_minutes: 0.0145 Virtual_time_in_hours: 0.000241667 Virtual_time_in_days: 0.000241667 Ruby_current_time: 26617001 Ruby_start_time: 1 Ruby_cycles: 26617000 mbytes_resident: 145.273 mbytes_total: 1330.63 resident_ratio: 0.109179 Total_misses: 0 total_misses: 0 [ 0 ] user_misses: 0 [ 0 ] supervisor_misses: 0 [ 0 ] instruction_executed: 1 [ 1 ] ruby_cycles_executed: 26617001 [ 26617001 ] cycles_per_instruction: 2.6617e+07 [ 2.6617e+07 ] misses_per_thousand_instructions: 0 [ 0 ] transactions_started: 0 [ 0 ] transactions_ended: 0 [ 0 ] instructions_per_transaction: 0 [ 0 ] cycles_per_transaction: 0 [ 0 ] misses_per_transaction: 0 [ 0 ] L1D_cache cache stats: L1D_cache_total_misses: 0 L1D_cache_total_demand_misses: 0 L1D_cache_total_prefetches: 0 L1D_cache_total_sw_prefetches: 0 L1D_cache_total_hw_prefetches: 0 L1D_cache_misses_per_transaction: 0 L1D_cache_misses_per_instruction: 0 L1D_cache_instructions_per_misses: NaN L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] L1I_cache cache stats: L1I_cache_total_misses: 0 L1I_cache_total_demand_misses: 0 L1I_cache_total_prefetches: 0 L1I_cache_total_sw_prefetches: 0 L1I_cache_total_hw_prefetches: 0 L1I_cache_misses_per_transaction: 0 L1I_cache_misses_per_instruction: 0 L1I_cache_instructions_per_misses: NaN L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] L2_cache cache stats: L2_cache_total_misses: 0 L2_cache_total_demand_misses: 0 L2_cache_total_prefetches: 0 L2_cache_total_sw_prefetches: 0 L2_cache_total_hw_prefetches: 0 L2_cache_misses_per_transaction: 0 L2_cache_misses_per_instruction: 0 L2_cache_instructions_per_misses: NaN L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Memory control: memory_total_requests: 1082 memory_reads: 557 memory_writes: 525 memory_refreshes: 10431 memory_total_request_delays: 1311 memory_delays_per_request: 1.21165 memory_delays_in_input_queue: 525 memory_delays_behind_head_of_bank_queue: 0 memory_delays_stalled_at_head_of_bank_queue: 786 memory_stalls_for_bank_busy: 180 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 memory_stalls_for_arbitration: 38 memory_stalls_for_bus: 546 memory_stalls_for_tfaw: 0 memory_stalls_for_read_write_turnaround: 22 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 58 43 53 51 67 43 40 32 18 19 34 51 41 46 28 10 31 8 8 12 42 34 9 20 10 25 44 26 25 58 55 41 Busy Controller Counts: L1Cache-0:0 Directory-0:0 DMA-0:0 Busy Bank Count:0 L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] L2TBE_usage: [binsize: 1 max: 1 count: 1082 average: 0.485213 | standard deviation: 0.500693 | 557 525 ] StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8873 average: 1 | standard deviation: 0 | 0 8873 ] store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 279 count: 8873 average: 12.5938 | standard deviation: 41.1326 | 0 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_1: [binsize: 2 max: 279 count: 6886 average: 9.86669 | standard deviation: 35.7801 | 0 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_2: [binsize: 2 max: 279 count: 1053 average: 24.4786 | standard deviation: 57.8541 | 0 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_3: [binsize: 2 max: 259 count: 934 average: 19.3009 | standard deviation: 51.067 | 0 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Request vs. RubySystem State Profile -------------------------------- filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- Total_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standard deviation: 0 | 1082 ] Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standard deviation: 0 | 1082 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 557 average: 0 | standard deviation: 0 | 557 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 525 average: 0 | standard deviation: 0 | 525 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Resource Usage -------------- page_size: 4096 user_time: 0 system_time: 0 page_reclaims: 37883 page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 48 Network Stats ------------- switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.000127033 links_utilized_percent_switch_0_link_0: 5.08134e-05 bw: 640000 base_latency: 1 links_utilized_percent_switch_0_link_1: 0.000203254 bw: 160000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 links_utilized_percent_switch_1: 0.000127033 links_utilized_percent_switch_1_link_0: 5.08134e-05 bw: 640000 base_latency: 1 links_utilized_percent_switch_1_link_1: 0.000203254 bw: 160000 base_latency: 1 outgoing_messages_switch_1_link_0_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 links_utilized_percent_switch_2: 0 links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1 links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 links_utilized_percent_switch_3: 0.000135502 links_utilized_percent_switch_3_link_0: 0.000203254 bw: 160000 base_latency: 1 links_utilized_percent_switch_3_link_1: 0.000203254 bw: 160000 base_latency: 1 links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1 outgoing_messages_switch_3_link_0_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1 --- DMA --- - Event Counts - ReadRequest 0 WriteRequest 0 Data 0 Ack 0 - Transitions - READY ReadRequest 0 <-- READY WriteRequest 0 <-- BUSY_RD Data 0 <-- BUSY_WR Ack 0 <-- --- Directory --- - Event Counts - GETX 557 GETS 0 PUTX 525 PUTX_NotOwner 0 DMA_READ 0 DMA_WRITE 0 Memory_Data 557 Memory_Ack 525 - Transitions - I GETX 557 I PUTX_NotOwner 0 <-- I DMA_READ 0 <-- I DMA_WRITE 0 <-- M GETX 0 <-- M PUTX 525 M PUTX_NotOwner 0 <-- M DMA_READ 0 <-- M DMA_WRITE 0 <-- M_DRD GETX 0 <-- M_DRD PUTX 0 <-- M_DWR GETX 0 <-- M_DWR PUTX 0 <-- M_DWRI Memory_Ack 0 <-- IM GETX 0 <-- IM GETS 0 <-- IM PUTX 0 <-- IM PUTX_NotOwner 0 <-- IM DMA_READ 0 <-- IM DMA_WRITE 0 <-- IM Memory_Data 557 MI GETX 0 <-- MI GETS 0 <-- MI PUTX 0 <-- MI PUTX_NotOwner 0 <-- MI DMA_READ 0 <-- MI DMA_WRITE 0 <-- MI Memory_Ack 525 ID GETX 0 <-- ID GETS 0 <-- ID PUTX 0 <-- ID PUTX_NotOwner 0 <-- ID DMA_READ 0 <-- ID DMA_WRITE 0 <-- ID Memory_Data 0 <-- ID_W GETX 0 <-- ID_W GETS 0 <-- ID_W PUTX 0 <-- ID_W PUTX_NotOwner 0 <-- ID_W DMA_READ 0 <-- ID_W DMA_WRITE 0 <-- ID_W Memory_Ack 0 <-- --- L1Cache --- - Event Counts - Load 1053 Ifetch 6886 Store 934 Data 557 Fwd_GETX 0 Inv 0 Replacement 525 Writeback_Ack 525 Writeback_Nack 0 - Transitions - I Load 140 I Ifetch 320 I Store 97 I Inv 0 <-- I Replacement 0 <-- II Writeback_Nack 0 <-- M Load 913 M Ifetch 6566 M Store 837 M Fwd_GETX 0 <-- M Inv 0 <-- M Replacement 525 MI Fwd_GETX 0 <-- MI Inv 0 <-- MI Writeback_Ack 525 IS Data 460 IM Data 97