---------- Begin Simulation Statistics ---------- sim_seconds 0.000727 # Number of seconds simulated sim_ticks 727072500 # Number of ticks simulated final_tick 727072500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 639322 # Simulator instruction rate (inst/s) host_op_rate 639300 # Simulator op (including micro ops) rate (op/s) host_tick_rate 929601467 # Simulator tick rate (ticks/s) host_mem_usage 223596 # Number of bytes of host memory used host_seconds 0.78 # Real time elapsed on the host sim_insts 500001 # Number of instructions simulated sim_ops 500001 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory system.physmem.bytes_read::total 54848 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 25792 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 25792 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory system.physmem.num_reads::total 857 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 35473766 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 39963002 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 75436769 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 35473766 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 35473766 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 35473766 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 39963002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 75436769 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 124435 # DTB read hits system.cpu.dtb.read_misses 8 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 124443 # DTB read accesses system.cpu.dtb.write_hits 56340 # DTB write hits system.cpu.dtb.write_misses 10 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 56350 # DTB write accesses system.cpu.dtb.data_hits 180775 # DTB hits system.cpu.dtb.data_misses 18 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 180793 # DTB accesses system.cpu.itb.fetch_hits 500020 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_accesses 500033 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 1454145 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 500001 # Number of instructions committed system.cpu.committedOps 500001 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses system.cpu.num_func_calls 14357 # number of times a function call or return occured system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls system.cpu.num_int_insts 474689 # number of integer instructions system.cpu.num_fp_insts 32 # number of float instructions system.cpu.num_int_register_reads 654286 # number of times the integer registers were read system.cpu.num_int_register_writes 371542 # number of times the integer registers were written system.cpu.num_fp_register_reads 32 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written system.cpu.num_mem_refs 180793 # number of memory refs system.cpu.num_load_insts 124443 # Number of load instructions system.cpu.num_store_insts 56350 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_busy_cycles 1454145 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 59023 # Number of branches fetched system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 500019 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 287.258890 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 287.258890 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits system.cpu.dcache.overall_hits::total 180321 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses system.cpu.dcache.overall_misses::total 454 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16852500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 16852500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7436500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 7436500 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24289000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 24289000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24289000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 24289000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 265.012564 # Cycle average of tags in use system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 265.012564 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.196777 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1000443 # Number of tag accesses system.cpu.icache.tags.data_accesses 1000443 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 499617 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 499617 # number of overall hits system.cpu.icache.overall_hits::total 499617 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 403 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 403 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses system.cpu.icache.overall_misses::total 403 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 22165500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 22165500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 22165500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 22165500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 22165500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 22165500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 500020 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55001.240695 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 55001.240695 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55001.240695 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 55001.240695 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55001.240695 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 55001.240695 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21561000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 21561000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21561000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 21561000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21561000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 21561000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000806 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000806 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53501.240695 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53501.240695 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53501.240695 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53501.240695 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 481.541188 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019216 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 216.521972 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 718 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 714 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021912 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7713 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7713 # Number of data accesses system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses system.cpu.l2cache.overall_misses::total 857 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21158000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16537500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 37695500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7297500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 7297500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 21158000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 23835000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 44993000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 21158000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 23835000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 44993000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 403 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.240695 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.696379 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.240695 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52500.583431 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.240695 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52500.583431 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 718 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16321500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12757500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 29079000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5629500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5629500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16321500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18387000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 34708500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16321500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18387000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 34708500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 718 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25792 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 857 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 857 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 857 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 604500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.trans_dist::ReadReq 718 # Transaction distribution system.membus.trans_dist::ReadResp 718 # Transaction distribution system.membus.trans_dist::ReadExReq 139 # Transaction distribution system.membus.trans_dist::ReadExResp 139 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 857 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 857 # Request fanout histogram system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 4285500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ----------