---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated sim_ticks 19589000 # Number of ticks simulated final_tick 19589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 1364 # Simulator instruction rate (inst/s) host_op_rate 2472 # Simulator op (including micro ops) rate (op/s) host_tick_rate 4967212 # Simulator tick rate (ticks/s) host_mem_usage 245432 # Number of bytes of host memory used host_seconds 3.94 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory system.physmem.bytes_read::total 26432 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory system.physmem.num_reads::total 413 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 891929144 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 457399561 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1349328705 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 891929144 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 891929144 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 891929144 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 457399561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1349328705 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 414 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 414 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 26432 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 26432 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 33 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 5 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 50 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 36 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.totGap 19541000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 414 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 249 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 216.275862 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 131.153640 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 325.056442 # Bytes accessed per row activation system.physmem.bytesPerActivate::64 43 49.43% 49.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 13 14.94% 64.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 9 10.34% 74.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 4 4.60% 79.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 7 8.05% 87.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::384 3 3.45% 90.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::512 1 1.15% 91.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::640 1 1.15% 93.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 1 1.15% 94.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::768 1 1.15% 95.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::960 2 2.30% 97.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::1344 1 1.15% 98.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368 1 1.15% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation system.physmem.totQLat 1394000 # Total cycles spent in queuing delays system.physmem.totMemAccLat 11081500 # Sum of mem lat for all requests system.physmem.totBusLat 2070000 # Total cycles spent in databus access system.physmem.totBankLat 7617500 # Total cycles spent in bank access system.physmem.avgQLat 3367.15 # Average queueing delay per request system.physmem.avgBankLat 18399.76 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 26766.91 # Average memory access latency system.physmem.avgRdBW 1349.33 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1349.33 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 10.54 # Data bus utilization in percentage system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 327 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 47200.48 # Average gap between requests system.membus.throughput 1349328705 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 337 # Transaction distribution system.membus.trans_dist::ReadResp 336 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution system.membus.trans_dist::ReadExResp 77 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 827 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 827 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.physmem.port 827 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 827 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 26432 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 26432 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 498000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) system.membus.respLayer1.occupancy 3864000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 19.7 # Layer utilization (%) system.cpu.branchPred.lookups 3089 # Number of BP lookups system.cpu.branchPred.condPredicted 3089 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 2286 # Number of BTB lookups system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 31.758530 # BTB Hit Percentage system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 39179 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 10273 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 14155 # Number of instructions fetch has processed system.cpu.fetch.Branches 3089 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3944 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 5406 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 375 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 21925 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.151015 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.666624 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 18081 82.47% 82.47% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 213 0.97% 83.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 143 0.65% 84.09% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 223 1.02% 85.11% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 185 0.84% 85.95% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 200 0.91% 86.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 277 1.26% 88.13% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 158 0.72% 88.85% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 2445 11.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 21925 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.078843 # Number of branch fetches per cycle system.cpu.fetch.rate 0.361290 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 11051 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 5299 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3578 # Number of cycles decode is running system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 24188 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 11417 # Number of cycles rename is idle system.cpu.rename.BlockCycles 3782 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 753 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 3333 # Number of cycles rename is running system.cpu.rename.UnblockCycles 783 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 22649 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 669 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 25230 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 54980 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 54964 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 14167 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 32 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 2073 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2281 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1568 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 20212 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 17024 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 9720 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 13890 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 21925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.776465 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.650682 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 16429 74.93% 74.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1551 7.07% 82.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 1089 4.97% 86.97% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 725 3.31% 90.28% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 705 3.22% 93.50% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 574 2.62% 96.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 578 2.64% 98.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 230 1.05% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 44 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 21925 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 139 76.80% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.80% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 27 14.92% 91.71% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 13662 80.25% 80.27% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.29% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 1972 11.58% 91.92% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1376 8.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 17024 # Type of FU issued system.cpu.iq.rate 0.434518 # Inst issue rate system.cpu.iq.fu_busy_cnt 181 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010632 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 56436 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 29967 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 15651 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 17198 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 173 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1228 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 633 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2975 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 20240 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 40 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2281 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1568 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 114 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 683 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 16133 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1855 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 891 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3133 # number of memory reference insts executed system.cpu.iew.exec_branches 1621 # Number of branches executed system.cpu.iew.exec_stores 1278 # Number of stores executed system.cpu.iew.exec_rate 0.411777 # Inst execution rate system.cpu.iew.wb_sent 15873 # cumulative count of insts sent to commit system.cpu.iew.wb_count 15655 # cumulative count of insts written-back system.cpu.iew.wb_producers 10119 # num instructions producing a value system.cpu.iew.wb_consumers 15566 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.399576 # insts written-back per cycle system.cpu.iew.wb_fanout 0.650071 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 10504 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 20068 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.485699 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.341238 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 16495 82.20% 82.20% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1364 6.80% 88.99% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 592 2.95% 91.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 713 3.55% 95.50% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 71 0.35% 98.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 213 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 20068 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1988 # Number of memory references committed system.cpu.commit.loads 1053 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 1208 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9654 # Number of committed integer instructions. system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 40106 # The number of ROB reads system.cpu.rob.rob_writes 42382 # The number of ROB writes system.cpu.timesIdled 168 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 17254 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated system.cpu.cpi 7.282342 # CPI: Cycles Per Instruction system.cpu.cpi_total 7.282342 # CPI: Total CPI of All Threads system.cpu.ipc 0.137318 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.137318 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 28721 # number of integer regfile reads system.cpu.int_regfile_writes 17199 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads system.cpu.misc_regfile_reads 7135 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.toL2Bus.throughput 1355862984 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 338 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 548 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 283 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count 831 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17536 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size 26560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 26560 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 411000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.tagsinuse 130.964375 # Cycle average of tags in use system.cpu.icache.total_refs 1611 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 274 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.879562 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 130.964375 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.063947 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.063947 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1611 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1611 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1611 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1611 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1611 # number of overall hits system.cpu.icache.overall_hits::total 1611 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 370 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 370 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 370 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 370 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 370 # number of overall misses system.cpu.icache.overall_misses::total 370 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 24285500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 24285500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 24285500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 24285500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 24285500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 24285500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186774 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.186774 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.186774 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.186774 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.186774 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.186774 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65636.486486 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 65636.486486 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 65636.486486 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 65636.486486 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 65636.486486 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 96 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 96 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 96 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 96 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 96 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 96 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18984000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 18984000 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18984000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 18984000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18984000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 18984000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138314 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.138314 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138314 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.138314 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69284.671533 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69284.671533 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69284.671533 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 69284.671533 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69284.671533 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 69284.671533 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 162.651714 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 336 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005952 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::cpu.inst 131.033866 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 31.617848 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.003999 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.004964 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 337 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 414 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 414 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18699000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4915000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 23614000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5418500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5418500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 18699000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10333500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 29032500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 18699000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10333500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 29032500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 274 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 416 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 274 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 416 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996350 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.984615 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.994100 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.992958 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.995192 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992958 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995192 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68494.505495 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76796.875000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 70071.216617 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70370.129870 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70370.129870 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68494.505495 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73287.234043 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 70126.811594 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68494.505495 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73287.234043 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 70126.811594 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 414 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 414 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15318750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4136000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19454750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4474750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4474750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15318750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8610750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 23929500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15318750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8610750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 23929500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984615 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994100 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992958 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.995192 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992958 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995192 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56112.637363 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64625 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57729.228487 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58113.636364 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58113.636364 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56112.637363 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61069.148936 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57800.724638 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56112.637363 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61069.148936 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57800.724638 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 81.657362 # Cycle average of tags in use system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 16.553191 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 81.657362 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.019936 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.019936 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1476 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1476 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 2334 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 2334 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 2334 # number of overall hits system.cpu.dcache.overall_hits::total 2334 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses system.cpu.dcache.overall_misses::total 208 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 9350500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 9350500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5649500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5649500 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 15000000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 15000000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 15000000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 15000000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1607 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1607 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 2542 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 2542 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2542 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2542 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081518 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.081518 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.081825 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.081825 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081825 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.081825 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71377.862595 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 71377.862595 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73370.129870 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 73370.129870 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 72115.384615 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 72115.384615 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 72115.384615 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4989000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4989000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5495500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5495500 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10484500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 10484500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10484500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10484500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040448 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040448 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.055862 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.055862 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76753.846154 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76753.846154 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71370.129870 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71370.129870 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------