---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBHits 606 # Number of BTB hits global.BPredUnit.BTBLookups 1858 # Number of BTB lookups global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted global.BPredUnit.lookups 2195 # Number of BP lookups global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. host_inst_rate 22780 # Simulator instruction rate (inst/s) host_mem_usage 154084 # Number of bytes of host memory used host_seconds 0.25 # Real time elapsed on the host host_tick_rate 14337041 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads. memdepunit.memDep.conflictingStores 138 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated sim_seconds 0.000004 # Number of seconds simulated sim_ticks 3543500 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.samples 6315 system.cpu.commit.COM:committed_per_cycle.min_value 0 0 4255 6737.93% 1 915 1448.93% 2 408 646.08% 3 162 256.53% 4 140 221.69% 5 91 144.10% 6 121 191.61% 7 102 161.52% 8 121 191.61% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 5640 # Number of instructions committed system.cpu.commit.COM:loads 979 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1857 # number of overall hits system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses system.cpu.dcache.overall_misses 471 # number of overall misses system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 7088 system.cpu.fetch.rateDist.min_value 0 0 4755 6708.52% 1 197 277.93% 2 177 249.72% 3 163 229.97% 4 234 330.14% 5 170 239.84% 6 198 279.35% 7 114 160.84% 8 1080 1523.70% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses system.cpu.icache.demand_misses 328 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1288 # number of overall hits system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses system.cpu.icache.overall_misses 328 # number of overall misses system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.iew.EXEC:branches 1203 # Number of branches executed system.cpu.iew.EXEC:nop 41 # number of nop insts executed system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed system.cpu.iew.EXEC:stores 989 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.WB:consumers 5598 # num instructions consuming a value system.cpu.iew.WB:count 7767 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 4153 # num instructions producing a value system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued IntAlu 5713 66.97% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued MemRead 1773 20.78% # Type of FU issued MemWrite 1040 12.19% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 7 5.47% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available MemRead 78 60.94% # attempts to use FU when none available MemWrite 43 33.59% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 7088 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 0 4068 5739.28% 1 771 1087.75% 2 763 1076.47% 3 485 684.26% 4 504 711.06% 5 295 416.20% 6 144 203.16% 7 40 56.43% 8 18 25.40% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 485 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 7088 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ----------