[root] type=Root children=system time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 [system.cpu] type=DerivO3CPU children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 cachePorts=200 checker=Null choiceCtrBits=2 choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 forwardComSize=5 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 phase=0 predType=tournament progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned smtIQThreshold=100 smtLSQPolicy=Partitioned smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 wbDepth=1 wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true hash_delay=1 is_top_level=true latency=1000 max_miss_count=0 mshrs=10 num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false repl=Null size=262144 subblock_size=0 tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc issueLat=1 opClass=IntAlu opLat=1 [system.cpu.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc issueLat=19 opClass=IntDiv opLat=20 [system.cpu.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=4 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc issueLat=1 opClass=FloatCvt opLat=2 [system.cpu.fuPool.FUList3] type=FUDesc children=opList0 opList1 opList2 count=2 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc issueLat=24 opClass=FloatSqrt opLat=24 [system.cpu.fuPool.FUList4] type=FUDesc children=opList count=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc issueLat=1 opClass=SimdFloatSqrt opLat=1 [system.cpu.fuPool.FUList6] type=FUDesc children=opList count=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 [system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 [system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess opLat=3 [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true hash_delay=1 is_top_level=true latency=1000 max_miss_count=0 mshrs=10 num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false repl=Null size=131072 subblock_size=0 tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] [system.cpu.itb] type=ArmTLB size=64 [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true hash_delay=1 is_top_level=false latency=1000 max_miss_count=0 mshrs=10 num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false repl=Null size=2097152 subblock_size=0 tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus block_size=64 bus_id=0 clock=1000 header_cycles=1 use_default_range=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 output=cout pid=100 ppid=99 simpoint=0 system=system uid=100 [system.membus] type=Bus block_size=64 bus_id=0 clock=1000 header_cycles=1 use_default_range=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= latency=30000 latency_var=0 null=false range=0:134217727 zero=false port=system.membus.port[0]