// -*- mode:c++ -*- //////////////////////////////////////////////////////////////////// // // The actual MIPS32 ISA decoder // ----------------------------- // The following instructions are specified in the MIPS32 ISA // Specification. Decoding closely follows the style specified // in the MIPS32 ISAthe specification document starting with Table // A-2 (document available @ www.mips.com) // //@todo: Distinguish "unknown/future" use insts from "reserved" // ones decode OPCODE_HI default Unknown::unknown() { // Derived From ... Table A-2 MIPS32 ISA Manual 0x0: decode OPCODE_LO { 0x0: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { 0x1: decode MOVCI { format BasicOp { 0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}}); 1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}}); } } format BasicOp { //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields //are used to distinguish among the SLL, NOP, SSNOP and EHB functions. 0x0: decode RS { 0x0: decode RT { //fix Nop traditional vs. Nop converted disassembly later 0x0: decode RD default Nop::nop(){ 0x0: decode SA { 0x1: ssnop({{ ; }}); //really sll r0,r0,1 0x3: ehb({{ ; }}); //really sll r0,r0,3 } } default: sll({{ Rd = Rt.uw << SA; }}); } } 0x2: decode RS_SRL { 0x0:decode SRL { 0: srl({{ Rd = Rt.uw >> SA; }}); //Hardcoded assuming 32-bit ISA, probably need parameter here 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); } } 0x3: decode RS { 0x0: sra({{ uint32_t temp = Rt >> SA; if ( (Rt & 0x80000000) > 0 ) { uint32_t mask = 0x80000000; for(int i=0; i < SA; i++) { temp |= mask; mask = mask >> 1; } } Rd = temp; }}); } 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 0x6: decode SRLV { 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); //Hardcoded assuming 32-bit ISA, probably need parameter here 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); } 0x7: srav({{ int shift_amt = Rs<4:0>; uint32_t temp = Rt >> shift_amt; if ( (Rt & 0x80000000) > 0 ) { uint32_t mask = 0x80000000; for(int i=0; i < shift_amt; i++) { temp |= mask; mask = mask >> 1; } } Rd = temp; }}); } } 0x1: decode FUNCTION_LO { //Table A-3 Note: "Specific encodings of the hint field are used //to distinguish JR from JR.HB and JALR from JALR.HB" format Jump { 0x0: decode HINT { 0:jr({{ NNPC = Rs & ~1; }},IsReturn); 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn); } 0x1: decode HINT { 0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn); 1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); } } format BasicOp { 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); } format BasicOp { 0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative); 0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative); 0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative); } } 0x2: decode FUNCTION_LO { format BasicOp { 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }}); 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }}); 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }}); 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }}); } } 0x3: decode FUNCTION_LO { format IntOp { 0x0: mult({{ int64_t temp1 = Rs.sd * Rt.sd; xc->setMiscReg(Hi,temp1<63:32>); xc->setMiscReg(Lo,temp1<31:0>); }}); 0x1: multu({{ uint64_t temp1 = Rs.ud * Rt.ud; xc->setMiscReg(Hi,temp1<63:32>); xc->setMiscReg(Lo,temp1<31:0>); }}); 0x2: div({{ xc->setMiscReg(Hi,Rs.sd % Rt.sd); xc->setMiscReg(Lo,Rs.sd / Rt.sd); }}); 0x3: divu({{ xc->setMiscReg(Hi,Rs.ud % Rt.ud); xc->setMiscReg(Lo,Rs.ud / Rt.ud); }}); } } 0x4: decode HINT { 0x0: decode FUNCTION_LO { format IntOp { 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}}); 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 0x4: and({{ Rd = Rs & Rt;}}); 0x5: or({{ Rd = Rs | Rt;}}); 0x6: xor({{ Rd = Rs ^ Rt;}}); 0x7: nor({{ Rd = ~(Rs | Rt);}}); } } } 0x5: decode HINT { 0x0: decode FUNCTION_LO { format IntOp{ 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); } } } 0x6: decode FUNCTION_LO { format Trap { 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); } } } 0x1: decode REGIMM_HI { 0x0: decode REGIMM_LO { format Branch { 0x0: bltz({{ cond = (Rs.sw < 0); }}); 0x1: bgez({{ cond = (Rs.sw >= 0); }}); } format BranchLikely { //MIPS obsolete instructions 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); } } 0x1: decode REGIMM_LO { format Trap { 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); } } 0x2: decode REGIMM_LO { format Branch { 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); } format BranchLikely { //Will be removed in future MIPS releases 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); } } 0x3: decode REGIMM_LO { format WarnUnimpl { 0x7: synci(); } } } format Jump { 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn); } format Branch { 0x4: beq({{ cond = (Rs.sw == Rt.sw); }}); 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 0x6: decode RT { 0x0: blez({{ cond = (Rs.sw <= 0); }}); } 0x7: decode RT { 0x0: bgtz({{ cond = (Rs.sw > 0); }}); } } } 0x1: decode OPCODE_LO { format IntOp { 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 0x7: decode RS { 0x0: lui({{ Rt = imm << 16}}); } } } 0x2: decode OPCODE_LO { //Table A-11 MIPS32 COP0 Encoding of rs Field 0x0: decode RS_MSB { 0x0: decode RS { format System { 0x0: mfc0({{ //uint64_t reg_num = Rd.uw; Rt = xc->readMiscReg(RD << 5 | SEL); }}); 0x4: mtc0({{ //uint64_t reg_num = Rd.uw; xc->setMiscReg(RD << 5 | SEL,Rt); }}); 0x8: mftr({{ //The contents of the coprocessor 0 register specified by the //combination of rd and sel are loaded into general register //rt. Note that not all coprocessor 0 registers support the //sel field. In those instances, the sel field must be zero. //MT Code Needed Here }}); 0xC: mttr({{ //The contents of the coprocessor 0 register specified by the //combination of rd and sel are loaded into general register //rt. Note that not all coprocessor 0 registers support the //sel field. In those instances, the sel field must be zero. //MT Code Needed Here }}); 0xA: rdpgpr({{ //Accessing Previous Shadow Set Register Number //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/; //uint64_t reg_num = Rt.uw; //Rd = xc->regs.IntRegFile[prev]; //Rd = xc->shadowIntRegFile[prev][reg_num]; }}); 0xB: decode RD { 0x0: decode SC { 0x0: dvpe({{ Rt.sw = xc->readMiscReg(MVPControl); xc->setMiscReg(MVPControl,0); }}); 0x1: evpe({{ Rt.sw = xc->readMiscReg(MVPControl); xc->setMiscReg(MVPControl,1); }}); } 0x1: decode SC { 0x0: dmt({{ Rt.sw = xc->readMiscReg(VPEControl); xc->setMiscReg(VPEControl,0); }}); 0x1: emt({{ Rt.sw = xc->readMiscReg(VPEControl); xc->setMiscReg(VPEControl,1); }}); } 0xC: decode SC { 0x0: di({{ Rt.sw = xc->readMiscReg(Status); xc->setMiscReg(Status,0); }}); 0x1: ei({{ Rt.sw = xc->readMiscReg(Status); xc->setMiscReg(Status,1); }}); } } 0xE: wrpgpr({{ //Accessing Previous Shadow Set Register Number //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/); //uint64_t reg_num = Rd.uw; //xc->regs.IntRegFile[prev]; //xc->shadowIntRegFile[prev][reg_num] = Rt; }}); } } //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 0x1: decode FUNCTION { format System { 0x01: tlbr({{ }}); 0x02: tlbwi({{ }}); 0x06: tlbwr({{ }}); 0x08: tlbp({{ }}); } format WarnUnimpl { 0x18: eret(); 0x1F: deret(); 0x20: wait(); } } } //Table A-13 MIPS32 COP1 Encoding of rs Field 0x1: decode RS_MSB { 0x0: decode RS_HI { 0x0: decode RS_LO { format FloatOp { 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }}); 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 0x7: mthc1({{ uint64_t fs_hi = Rt.ud << 32; uint64_t fs_lo = Fs.ud & 0x0000FFFF; Fs.ud = fs_hi & fs_lo; }}); } format System { 0x2: cfc1({{ uint32_t fcsr_reg = xc->readMiscReg(FCSR); switch (FS) { case 0: Rt = xc->readMiscReg(FIR); break; case 25: Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23; break; case 26: Rt = 0 | (fcsr_reg & 0x0003F07C); break; case 28: Rt = 0 | (fcsr_reg); break; case 31: Rt = fcsr_reg; break; default: panic("FP Control Value (%d) Not Available. Ignoring Access to" "Floating Control Status Register",fcsr_reg); } }}); 0x6: ctc1({{ uint32_t fcsr_reg = xc->readMiscReg(FCSR); uint32_t temp; switch (FS) { case 25: temp = 0 | (Rt.uw<7:1> << 25) // move 31...25 | (fcsr_reg & 0x01000000) // bit 24 | (fcsr_reg & 0x004FFFFF);// bit 22...0 break; case 26: temp = 0 | (fcsr_reg & 0xFFFC0000) // move 31...18 | Rt.uw<17:12> << 12 // bit 17...12 | (fcsr_reg & 0x00000F80) << 7// bit 11...7 | Rt.uw<6:2> << 2 // bit 6...2 | (fcsr_reg & 0x00000002); // bit 1...0 break; case 28: temp = 0 | (fcsr_reg & 0xFE000000) // move 31...25 | Rt.uw<2:2> << 24 // bit 24 | (fcsr_reg & 0x00FFF000) << 23// bit 23...12 | Rt.uw<11:7> << 7 // bit 24 | (fcsr_reg & 0x000007E) | Rt.uw<1:0>;// bit 22...0 break; case 31: temp = Rt.uw; break; default: panic("FP Control Value (%d) Not Available. Ignoring Access to" "Floating Control Status Register",fcsr_reg); } xc->setMiscReg(FCSR,temp); }}); } } 0x1: decode ND { 0x0: decode TF { format Branch { 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }}); } } 0x1: decode TF { format BranchLikely { 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }}); } } } } 0x1: decode RS_HI { 0x2: decode RS_LO { //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S //(( single-word )) 0x0: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format FloatOp { 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 0x5: abss({{ Fd.sf = fabs(Fs.sf);}}); 0x6: movs({{ Fd.sf = Fs.sf;}}); 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); } } 0x1: decode FUNCTION_LO { format Float64Op { 0x0: round_l_s({{ Fd = convert_and_round(Fs.uw, SINGLE_TO_LONG, RND_NEAREST); }}); 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.uw, SINGLE_TO_LONG, RND_ZERO); }}); 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.uw, SINGLE_TO_LONG, RND_UP); }}); 0x3: floor_l_s({{ Fd = convert_and_round(Fs.uw, SINGLE_TO_LONG, RND_DOWN); }}); } format FloatOp { 0x4: round_w_s({{ Fd = convert_and_round(Fs.uw, SINGLE_TO_WORD, RND_NEAREST); }}); 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.uw, SINGLE_TO_WORD, RND_ZERO); }}); 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.uw, SINGLE_TO_WORD, RND_UP); }}); 0x7: floor_w_s({{ Fd = convert_and_round(Fs.uw, SINGLE_TO_WORD, RND_DOWN); }}); } } 0x2: decode FUNCTION_LO { 0x1: decode MOVCF { format FloatOp { 0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); } } format BasicOp { 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); } format Float64Op { 0x5: recips({{ Fd = 1 / Fs; }}); 0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}}); } } 0x4: decode FUNCTION_LO { format FloatOp { 0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_DOUBLE, rnd_mode); }}); 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.uw = convert_and_round(Fs.uw, SINGLE_TO_WORD, rnd_mode); }}); } //only legal for 64 bit format Float64Op { 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.ud = convert_and_round(Fs.uw, SINGLE_TO_LONG, rnd_mode); }}); 0x6: cvt_ps_st({{ Fd.ud = (uint64_t)Fs.uw << 32 | (uint64_t)Ft.uw; }}); } } } //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 0x1: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format FloatOp { 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 0x5: absd({{ Fd.df = fabs(Fs.df);}}); 0x6: movd({{ Fd.ud = Fs.ud;}}); 0x7: negd({{ Fd.df = -1 * Fs.df;}}); } } 0x1: decode FUNCTION_LO { format Float64Op { 0x0: round_l_d({{ Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_NEAREST); }}); 0x1: trunc_l_d({{ Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_ZERO); }}); 0x2: ceil_l_d({{ Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_UP); }}); 0x3: floor_l_d({{ Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_DOWN); }}); } format FloatOp { 0x4: round_w_d({{ Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_NEAREST); }}); 0x5: trunc_w_d({{ Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_ZERO); }}); 0x6: ceil_w_d({{ Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_UP); }}); 0x7: floor_w_d({{ Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_DOWN); }}); } } 0x2: decode FUNCTION_LO { 0x1: decode MOVCF { format FloatOp { 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }}); 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }}); } } format BasicOp { 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); } format Float64Op { 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); } } 0x4: decode FUNCTION_LO { format FloatOp { 0x0: cvt_s_d({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_SINGLE, rnd_mode); }}); 0x4: cvt_w_d({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, rnd_mode); }}); } //only legal for 64 bit format Float64Op { 0x5: cvt_l_d({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, rnd_mode); }}); } } } //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 0x4: decode FUNCTION { format FloatOp { 0x20: cvt_s_w({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.uw = convert_and_round(Fs.uw, WORD_TO_SINGLE, rnd_mode); }}); 0x21: cvt_d_w({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.ud = convert_and_round(Fs.uw, WORD_TO_DOUBLE, rnd_mode); }}); } } //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 //Note: "1. Format type L is legal only if 64-bit floating point operations //are enabled." 0x5: decode FUNCTION_HI { format Float64Op { 0x10: cvt_s_l({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.uw = convert_and_round(Fs.ud, LONG_TO_SINGLE, rnd_mode); }}); 0x11: cvt_d_l({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.ud = convert_and_round(Fs.ud, LONG_TO_DOUBLE, rnd_mode); }}); } } //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 //Note: "1. Format type PS is legal only if 64-bit floating point operations //are enabled. " 0x6: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format Float64Op { 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut Fd.df = Fs.df + Ft.df; }}); 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut Fd.df = Fs.df - Ft.df; }}); 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut Fd.df = Fs.df * Ft.df; }}); 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut Fd.df = fabs(Fs.df); }}); 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut //Fd.df = Fs<31:0> | Ft<31:0>; }}); 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut Fd.df = -1 * Fs.df; }}); } } 0x2: decode FUNCTION_LO { 0x1: decode MOVCF { format Float64Op { 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}}); 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); } } format BasicOp { 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }}); } } 0x4: decode FUNCTION_LO { 0x0: Float64Op::cvt_s_pu({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.uw = convert_and_round(Fs.ud, PUPPER_TO_SINGLE, rnd_mode); }}); } 0x5: decode FUNCTION_LO { format Float64Op { 0x0: cvt_s_pl({{ int rnd_mode = xc->readMiscReg(FCSR) & 0x03; Fd.uw = convert_and_round(Fs.ud, PLOWER_TO_SINGLE, rnd_mode); }}); 0x4: pll({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<31:0>; }}); 0x5: plu({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>;}}); 0x6: pul({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<31:0>; }}); 0x7: puu({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<63:32>;}}); } } } } } } //Table A-19 MIPS32 COP2 Encoding of rs Field 0x2: decode RS_MSB { 0x0: decode RS_HI { 0x0: decode RS_LO { format WarnUnimpl { 0x0: mfc2(); 0x2: cfc2(); 0x3: mfhc2(); 0x4: mtc2(); 0x6: ctc2(); 0x7: mftc2(); } } 0x1: decode ND { 0x0: decode TF { format WarnUnimpl { 0x0: bc2f(); 0x1: bc2t(); } } 0x1: decode TF { format WarnUnimpl { 0x0: bc2fl(); 0x1: bc2tl(); } } } } } //Table A-20 MIPS64 COP1X Encoding of Function Field 1 //Note: "COP1X instructions are legal only if 64-bit floating point //operations are enabled." 0x3: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format LoadFloatMemory { 0x0: lwxc1({{ /*F_t<31:0> = Mem.sf; */}}, {{ EA = Rs + Rt; }}); 0x1: ldxc1({{ /*F_t<63:0> = Mem.df;*/ }}, {{ EA = Rs + Rt; }}); 0x5: luxc1({{ /*F_t<31:0> = Mem.df; */}}, {{ //Need to make EA<2:0> = 0 EA = Rs + Rt; }}); } } 0x1: decode FUNCTION_LO { format StoreFloatMemory { 0x0: swxc1({{ /*Mem.sf = Ft<31:0>; */}},{{ EA = Rs + Rt; }}); 0x1: sdxc1({{ /*Mem.df = Ft<63:0> */}}, {{ EA = Rs + Rt; }}); 0x5: suxc1({{ /*Mem.df = F_t<63:0>;*/}}, {{ //Need to make sure EA<2:0> = 0 EA = Rs + Rt; }}); } 0x7: WarnUnimpl::prefx(); } format FloatOp { 0x3: WarnUnimpl::alnv_ps(); format BasicOp { 0x4: decode FUNCTION_LO { 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 0x6: madd_ps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut Fd.df = (Fs.df * Fs.df) + Fr.df; }}); } 0x5: decode FUNCTION_LO { 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 0x6: msub_ps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut Fd.df = (Fs.df * Fs.df) - Fr.df; }}); } 0x6: decode FUNCTION_LO { 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 0x6: nmadd_ps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); } 0x7: decode FUNCTION_LO { 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 0x6: nmsub_ps({{ //Must Check for Exception Here... Supposed to Operate on Upper and //Lower Halves Independently but we take simulator shortcut Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); } } } } //MIPS obsolete instructions format BranchLikely { 0x4: beql({{ cond = (Rs.sw == 0); }}); 0x5: bnel({{ cond = (Rs.sw != 0); }}); 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); } } 0x3: decode OPCODE_LO default FailUnimpl::reserved() { //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 0x4: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format IntOp { 0x0: madd({{ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; temp1 = temp1 + (Rs.sw * Rt.sw); xc->setMiscReg(Hi,temp1<63:32>); xc->setMiscReg(Lo,temp1<31:0>); }}); 0x1: maddu({{ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; temp1 = temp1 + (Rs.uw * Rt.uw); xc->setMiscReg(Hi,temp1<63:32>); xc->setMiscReg(Lo,temp1<31:0>); }}); 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 0x4: msub({{ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; temp1 = temp1 - (Rs.sw * Rt.sw); xc->setMiscReg(Hi,temp1<63:32>); xc->setMiscReg(Lo,temp1<31:0>); }}); 0x5: msubu({{ int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; temp1 = temp1 - (Rs.uw * Rt.uw); xc->setMiscReg(Hi,temp1<63:32>); xc->setMiscReg(Lo,temp1<31:0>); }}); } } 0x4: decode FUNCTION_LO { format BasicOp { 0x0: clz({{ /*int cnt = 0; int idx = 0; while ( Rs.uw != 1) { cnt++; idx--; } Rd.uw = cnt;*/ }}); 0x1: clo({{ /*int cnt = 0; int idx = 0; while ( Rs.uw != 0) { cnt++; idx--; } Rd.uw = cnt;*/ }}); } } 0x7: decode FUNCTION_LO { 0x7: WarnUnimpl::sdbbp(); } } //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 0x7: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format FailUnimpl { 0x1: ext(); 0x4: ins(); } } 0x1: decode FUNCTION_LO { format FailUnimpl { 0x0: fork(); 0x1: yield(); } } //Table A-10 MIPS32 BSHFL Encoding of sa Field 0x4: decode SA { 0x02: FailUnimpl::wsbh(); format BasicOp { 0x10: seb({{ Rd.sw = Rt<7:0>}}); 0x18: seh({{ Rd.sw = Rt<15:0>}}); } } 0x6: decode FUNCTION_LO { 0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }} } } } 0x4: decode OPCODE_LO default FailUnimpl::reserved() { format LoadMemory { 0x0: lb({{ Rt.sw = Mem.sb; }}); 0x1: lh({{ Rt.sw = Mem.sh; }}); 0x2: lwl({{ uint32_t mem_word = Mem.uw; uint32_t unalign_addr = Rs + disp; uint32_t offset = unalign_addr & 0x00000003; #if BYTE_ORDER == BIG_ENDIAN std::cout << "Big Endian Byte Order\n"; switch(offset) { case 0: Rt = mem_word; break; case 1: Rt &= 0x000F; Rt |= (mem_word << 4); break; case 2: Rt &= 0x00FF; Rt |= (mem_word << 8); break; case 3: Rt &= 0x0FFF; Rt |= (mem_word << 12); break; default: panic("lwl: bad offset"); } #elif BYTE_ORDER == LITTLE_ENDIAN std::cout << "Little Endian Byte Order\n"; switch(offset) { case 0: Rt &= 0x0FFF; Rt |= (mem_word << 12); break; case 1: Rt &= 0x00FF; Rt |= (mem_word << 8); break; case 2: Rt &= 0x000F; Rt |= (mem_word << 4); break; case 3: Rt = mem_word; break; default: panic("lwl: bad offset"); } #endif }}, {{ EA = (Rs + disp) & ~3; }}); 0x3: lw({{ Rt.sw = Mem.sw; }}); 0x4: lbu({{ Rt.uw = Mem.ub; }}); 0x5: lhu({{ Rt.uw = Mem.uh; }}); 0x6: lwr({{ uint32_t mem_word = Mem.uw; uint32_t unalign_addr = Rs + disp; uint32_t offset = unalign_addr & 0x00000003; #if BYTE_ORDER == BIG_ENDIAN switch(offset) { case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break; case 3: Rt = mem_word; break; default: panic("lwr: bad offset"); } #elif BYTE_ORDER == LITTLE_ENDIAN switch(offset) { case 0: Rt = mem_word; break; case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break; case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; default: panic("lwr: bad offset"); } #endif }}, {{ EA = (Rs + disp) & ~3; }}); } 0x7: FailUnimpl::reserved(); } 0x5: decode OPCODE_LO default FailUnimpl::reserved() { format StoreMemory { 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 0x2: swl({{ uint32_t mem_word = 0; uint32_t aligned_addr = (Rs + disp) & ~3; uint32_t unalign_addr = Rs + disp; uint32_t offset = unalign_addr & 0x00000003; DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x", aligned_addr,unalign_addr,offset); fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); #if BYTE_ORDER == BIG_ENDIAN switch(offset) { case 0: Mem = Rt; break; case 1: mem_word &= 0xF000; mem_word |= (Rt >> 4); Mem = mem_word; break; case 2: mem_word &= 0xFF00; mem_word |= (Rt >> 8); Mem = mem_word; break; case 3: mem_word &= 0xFFF0; mem_word |= (Rt >> 12); Mem = mem_word; break; default: panic("swl: bad offset"); } #elif BYTE_ORDER == LITTLE_ENDIAN switch(offset) { case 0: mem_word &= 0xFFF0; mem_word |= (Rt >> 12); Mem = mem_word; break; case 1: mem_word &= 0xFF00; mem_word |= (Rt >> 8); Mem = mem_word; break; case 2: mem_word &= 0xF000; mem_word |= (Rt >> 4); Mem = mem_word; break; case 3: Mem = Rt; break; default: panic("swl: bad offset"); } #endif }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT); 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 0x6: swr({{ uint32_t mem_word = 0; uint32_t aligned_addr = (Rs + disp) & ~3; uint32_t unalign_addr = Rs + disp; uint32_t offset = unalign_addr & 0x00000003; fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); #if BYTE_ORDER == BIG_ENDIAN switch(offset) { case 0: mem_word &= 0x0FFF; mem_word |= (Rt << 12); Mem = mem_word; break; case 1: mem_word &= 0x00FF; mem_word |= (Rt << 8); Mem = mem_word; break; case 2: mem_word &= 0x000F; mem_word |= (Rt << 4); Mem = mem_word; break; case 3: Mem = Rt; break; default: panic("swr: bad offset"); } #elif BYTE_ORDER == LITTLE_ENDIAN switch(offset) { case 0: Mem = Rt; break; case 1: mem_word &= 0x000F; mem_word |= (Rt << 4); Mem = mem_word; break; case 2: mem_word &= 0x00FF; mem_word |= (Rt << 8); Mem = mem_word; break; case 3: mem_word &= 0x0FFF; mem_word |= (Rt << 12); Mem = mem_word; break; default: panic("swr: bad offset"); } #endif }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT); } format WarnUnimpl { 0x7: cache(); } } 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 0x0: FailUnimpl::ll(); format LoadFloatMemory { 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 0x5: ldc1({{ Ft.ud = Mem.ud; }}); } } 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 0x0: FailUnimpl::sc(); format StoreFloatMemory { 0x1: swc1({{ Mem.uw = Ft.uw; }}); 0x5: sdc1({{ Mem.ud = Ft.ud; }}); } } }