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# Authors: Prakash Ramrakhyani

from m5.params import *
from m5.proxy import *
from ClockedObject import ClockedObject

class BaseTags(ClockedObject):
    type = 'BaseTags'
    abstract = True
    cxx_header = "mem/cache/tags/base.hh"
    # Get the size from the parent (cache)
    size = Param.MemorySize(Parent.size, "capacity in bytes")

    # Get the block size from the parent (system)
    block_size = Param.Int(Parent.cache_line_size, "block size in bytes")

    # Get the tag lookup latency from the parent (cache)
    tag_latency = Param.Cycles(Parent.tag_latency,
                               "The tag lookup latency for this cache")

    # Get the RAM access latency from the parent (cache)
    data_latency = Param.Cycles(Parent.data_latency,
                               "The data access latency for this cache")

    sequential_access = Param.Bool(Parent.sequential_access,
        "Whether to access tags and data sequentially")

class BaseSetAssoc(BaseTags):
    type = 'BaseSetAssoc'
    abstract = True
    cxx_header = "mem/cache/tags/base_set_assoc.hh"
    assoc = Param.Int(Parent.assoc, "associativity")

class LRU(BaseSetAssoc):
    type = 'LRU'
    cxx_class = 'LRU'
    cxx_header = "mem/cache/tags/lru.hh"

class RandomRepl(BaseSetAssoc):
    type = 'RandomRepl'
    cxx_class = 'RandomRepl'
    cxx_header = "mem/cache/tags/random_repl.hh"

class FALRU(BaseTags):
    type = 'FALRU'
    cxx_class = 'FALRU'
    cxx_header = "mem/cache/tags/fa_lru.hh"

class NMRU(BaseSetAssoc):
    type = 'NMRU'
    cxx_class = 'NMRU'
    cxx_header = "mem/cache/tags/nmru.hh"

class LFU(BaseSetAssoc):
    type = 'LFU'
    cxx_class = 'LFU'
    cxx_header = "mem/cache/tags/lfu.hh"

class LIFO(BaseSetAssoc):
    type = 'LIFO'
    cxx_class = 'LIFO'
    cxx_header = "mem/cache/tags/lifo.hh"
class FIFO(BaseSetAssoc):
    type = 'FIFO'
    cxx_class = 'FIFO'
    cxx_header = "mem/cache/tags/fifo.hh"