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804 commits

Author SHA1 Message Date
Andreas Sandberg
f385adc8af tests: Add test infrastructure as a Python module
Implement gem5's test infrastructure as a Python module and a run
script that can be used without scons. The new implementation has
several features that were lacking from the previous test
infrastructure such as support for multiple output formats, automatic
runtime tracking, and better support for being run in a cluster
environment.

Tests consist of one or more steps (TestUnit). Units are run in two
stages, the first a run stage and then a verify stage. Units in the
verify stage are automatically skipped if any unit run stage wasn't
run. The library currently contains TestUnit implementations that run
gem5, diff stat files, and diff output files.

Existing tests are implemented by the ClassicTest class and "just
work". New tests can that don't rely on the old "run gem5 once and
diff output" strategy can be implemented by subclassing the Test base
class or ClassicTest.

Test results can be output in multiple formats. The module currently
supports JUnit, text (short and verbose), and Python's pickle
format. JUnit output allows CI systems to automatically get more
information about test failures. The pickled output contains all state
necessary to reconstruct a tests results object and is mainly intended
for the build system and CI systems.

Since many JUnit parsers parsers assume that test suite names look
like Java package names. We currently output path-like names with
slashes separating components. Test names are translated according to
these rules:

  * '.' -> '-"
  * '/' -> '.'

The test tool, tests.py, supports the following features:

  * Test listing. Example: ./tests.py list arm/quick

  * Running tests. Example:
    ./tests.py run -o output.pickle --format pickle \
        ../build/ARM/gem5.opt \
        quick/se/00.hello/arm/linux/simple-timing

  * Displaying pickled results. Example:
    ./tests.py show --format summary *.pickle

Change-Id: I527164bd791237aacfc65e7d7c0b67b695c5d17c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Joel Hestness <jthestness@gmail.com>
2016-05-26 11:56:24 +01:00
Andreas Sandberg
8b412fcfd6 tests: Enable test running outside of gem5's source tree
The learning gem5 scripts currently assumes that the current working
directory is the root of gem5's source tree. This isn't necessarily
the case when running the tests using gem5's new test runner.

Change-Id: Ief569bbe77b1b3e2b0fb0e6c575fb0705bbba9b3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-05-09 11:32:07 +01:00
Steve Reinhardt
2ae8b365c1 tests: update EIO ref stats for removed cache stats
Complaints about changes in EIO tests were due to reference files
that still have removed cache stats from cset 11454:e55afadc4e19.
2016-05-07 14:43:06 -04:00
Andreas Sandberg
b80f568bcf tests: Remove stale reference output files
Remove test reference files that are not generated any more:

    * chair.cook.ppm: This file should be generated by eon and not
      mcf, so it shouldn't be included as an output from mcf.

    * system.pc.terminal: The terminal device has been renamed so this
      file is no longer generated.

Change-Id: I3962efe1ff25479ca276115f7564eccb5fac8cf9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-04-28 15:16:52 +01:00
Andreas Hansson
8845aae4da tests: Add a basic memcheck regression
This patch adds a simple regression that calls the existing
memcheck.py script.

--HG--
rename : tests/configs/learning-gem5-p1-simple.py => tests/configs/memcheck.py
rename : tests/quick/se/70.tgen/test.py => tests/quick/se/51.memcheck/test.py
2016-04-25 03:46:12 -04:00
Jason Power
bf7e27fe45 tests: Update learning gem5 tests scripts with copyright 2016-04-21 17:25:31 -05:00
Andreas Hansson
b006ad26d4 stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
2016-04-21 04:48:24 -04:00
Andreas Hansson
d9193d1b20 stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
2016-04-09 12:13:40 -04:00
Curtis Dunham
1d61224a8b stats: update stats for thermals, indirect BP 2016-04-08 11:01:45 -05:00
Steve Reinhardt
d7c083864c stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
2016-03-17 10:32:53 -07:00
Steve Reinhardt
4fc69db8f8 stats: update stats for mmap changes 2016-03-17 10:30:58 -07:00
Steve Reinhardt
9d8fec0d90 stats: update stats for mmap() change.
SE O3 runs see an additional reg read per mmap() call.
2016-03-17 10:25:11 -07:00
Andreas Hansson
7a40e7864a stats: Bump stats to match cache changes
Update stats to match current behaviour. As a result of the earlier
conflict check we are seeing a few prefetch requests being ignored
before being sent as upward snoops.
2016-03-17 09:51:21 -04:00
Steve Reinhardt
f5d1dd75e5 stats: overdue updates to long regressions 2016-03-16 13:03:49 -07:00
Steve Reinhardt
807e2705b4 stats: update gpu-ruby-GPU_RfO stats
Output changed way back in this cset:

changeset:   11345:b6a66a90e0a1
user:        John Kalamatianos <john.kalamatianos@amd.com>
summary:     gpu: fix bugs with MemFence, Flat Instrs and Resource utilization
2016-02-18 10:42:03 -05:00
Krishnendra Nathella
cabd4768c7 cpu: Fix LLSC atomic CPU wakeup
Writes to locked memory addresses (LLSC) did not wake up the locking
CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU,
recvAtomicSnoop was checking if the incoming packet was an invalidation
(isInvalidate) and only then handled a locked snoop. But, writes are
seen instead of invalidates when running without caches (fast-forward
configurations). As as simple fix, now handleLockedSnoop is also called
even if the incoming snoop packet are from writes.
2015-07-19 15:03:30 -05:00
Andreas Hansson
28289e5995 stats: Update stats to reflect forwarding of InvalidateReq 2016-02-24 04:16:59 -05:00
Matteo Andreozzi
496a8c6c92 cpu: TraceGen fix for tick frequency check
Bug fix for check on protobuf file frequency being different than
global frequency.

The ASCII encoder script is also fixed, and the example trace used in
the regressions is updated.
2016-02-24 04:16:55 -05:00
Andreas Hansson
c6cede244b stats: Update stats to reflect changes to cache and crossbar 2016-02-10 04:08:27 -05:00
Steve Reinhardt
5592798865 style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'.
2016-02-06 17:21:19 -08:00
Steve Reinhardt
dc8018a5c3 style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-02-06 17:21:18 -08:00
Steve Reinhardt
ce35c06c6e stats: update EIO stats for recent changes 2016-02-06 01:35:03 -05:00
Tony Gutierrez
1285d639eb stats: update stats to after GPU checkin 2016-01-22 10:42:13 -05:00
Brad Beckmann
97a5e5b25e ruby: changed all references to numCPs to num-cp 2016-01-22 10:42:12 -05:00
Tony Gutierrez
1a7d3f9fcb gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
Steve Reinhardt
fcfe6e798d stats: update SPARC FS stats
The fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic test was
broken for so long that, now that it's working again, the stats
output is out of date.  This changeset updates the outputs, on
the assumption that the stats changes are all valid differences
due to other changes made while it was broken.
2016-01-17 21:13:29 -05:00
Steve Reinhardt
3840a72f37 stats: more updates due to PCI changes
A couple of the long regressions have been showing as CHANGED
since 11244:a2af58a06c4e despite the updates in 11245:1c5102c0a7a9.
The x86 regression looks like it was just missed, but it's not clear
why the ARM one is giving different results (perhaps a non-determinism
between zizzer and wherever the updated results were run?).
2015-12-30 11:18:44 -05:00
Steve Reinhardt
2b49d3b6ca tests: update EIO reference outputs 2015-12-28 15:43:06 -05:00
Anthony Gutierrez
4935f0d5ff stats: bump stats to reflect ruby tester changes 2015-12-12 17:27:38 -05:00
Brad Beckmann
634f34d3f2 regress: updates required for the compute-gpu patches 2015-12-11 16:07:01 -05:00
Andreas Sandberg
bbcbe028fe stats: Update to reflect changes to PCI handling 2015-12-05 00:11:25 +00:00
Andreas Sandberg
5a249e03a4 stats: Update to reflect changes to RealView platform code 2015-12-04 00:19:05 +00:00
Andreas Hansson
00b2bd7437 stats: Bump stats to match current behaviour 2015-12-02 09:58:24 -05:00
Nilay Vaish
de489e1997 stats: updates due to recent chagnesets 2015-11-16 05:08:57 -06:00
Nilay Vaish
e1385784f2 stats: remove wb_penalized and wb_penalized_rate 2015-11-16 04:58:29 -06:00
Andreas Hansson
324bc9771d stats: Update stats to match cache changes 2015-11-06 03:26:50 -05:00
Joel Hestness
735c4a8766 stats: Update for UDelayEvent quiesce change 2015-10-10 16:45:41 -05:00
Andreas Sandberg
17dbb49294 tests: Update SMT tests to correctly configure CPUs
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.

--HG--
rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
2015-10-05 13:13:23 -05:00
Steve Reinhardt
d1811cc6cf stats: update EIO stats for snoop filter changes 2015-10-02 01:04:12 -04:00
Mitch Hayenga
a5c4eb3de9 isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
582a0148b4 config,cpu: Add SMT support to Atomic and Timing CPUs
Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.
2015-09-30 11:14:19 -05:00
Andreas Hansson
806e1fbf0f stats: Update stats to reflect snoop-filter changes 2015-09-25 07:27:03 -04:00
Nilay Vaish
928d4b4ba8 stats: updates due to changes to MOESI_hammer 2015-09-16 22:17:54 -05:00
Nilay Vaish
c5058c0c00 stats: slight changes to MOESI_CMP_token.
Due slight change to latency for the reissue table.
2015-09-16 11:59:57 -05:00
Jason Lowe-Power
fdf2a6f439 stats: files for regression tests for Learning gem5 scripts
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-16 09:35:36 -05:00
Jason Lowe-Power
29dd04cfe9 tests: Add tests for the Learning gem5 scripts
These tests will ensure that Learning gem5 scripts are always up to date with
the changes in the mainline of gem5.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-16 09:35:36 -05:00
Nilay Vaish
0d6a6dfd7b stats: updates due to recent changesets including d0934b57735a 2015-09-15 08:14:09 -05:00
Nilay Vaish
66941163e5 stats: updates due to recent changes. 2015-08-30 12:24:19 -05:00
Nilay Vaish
d383a08f16 stats: updates to ruby fs regression test
Changes due to recent patches: fc1e41e88fd3, 882ce080c9f7, e8a6637afa4c, and
e6e3b7097810 by Joel Hestness.
2015-08-14 19:26:43 -05:00
Joel Hestness
93c173a95e stats: Bump for MessageBuffer, cache latency changes 2015-08-14 01:19:34 -05:00