Commit graph

8 commits

Author SHA1 Message Date
Ali Saidi
62f5d7dd3f move stuff around so PageShift is defined before it is needed
don't ever include a file while in a namespace
start of making alpha console new memsystem happy
Make a BasePioDevice which is what all the simple Pio devices will inherit from
add a description of when the data pointer will have memory

arch/alpha/isa_traits.hh:
    don't ever include a file while in a namespace
dev/alpha_console.cc:
dev/alpha_console.hh:
    start of making alpha console new memsystem happy
dev/io_device.cc:
dev/io_device.hh:
    Make a BasePioDevice which is what all the simple Pio devices will inherit from
mem/packet.hh:
    add a description of when the data pointer will have memory

--HG--
extra : convert_revision : 495c0915541f9cad3eb42891e60b4ecbee7952bf
2006-03-29 17:37:25 -05:00
Ali Saidi
b38f67d5b7 Implement a very very simple bus
requestTime -> time
responseTime -> packet.time

Make CPU and memory able to connect to the bus

dev/io_device.cc:
    update for request and packet both having a time
    hand platform off to port for eventual selection of request modes
dev/io_device.hh:
    update for request and packet both havig a time
    hand platform off to port for eventual selection of request modes
mem/bus.hh:
    Add a device map struct that maps a range to a portId
    - Which needs work it theory it should be an interval tree
    - but it is a list and works fine right now

    Add a function called findPort which returns port for an addr range

    Add a deviceBlockSize function that really shouldn't exist, but it
    was easier than fixing the translating port
mem/packet.hh:
    add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
    Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
    remove requestTime/responseTime for just time in request which
    is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
    Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
    Fix for new bus object

--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
2006-03-25 18:31:20 -05:00
Ali Saidi
8654cfa427 Make PioPort/DmaPort,DmaDevice/PioDevice compile.
Add another type to the PacketResult enum of Unknown
Seperate time into requsetTime and responseTime.

dev/io_device.cc:
dev/io_device.hh:
    Make PioPort/DmaPort,DmaDevice/PioDevice compile.
mem/packet.hh:
    Add another type to the PacketResult enum of Unknown (e.g. no state set yet)
mem/request.hh:
    Seperate time into requsetTime and responseTime.

--HG--
extra : convert_revision : c6394cb838013296caea6492275252b8cae2882f
2006-03-21 15:45:31 -05:00
Gabe Black
f102365bfe SimpleCPU compiles with merge.
arch/alpha/isa_traits.hh:
arch/alpha/linux/process.cc:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
base/chunk_generator.hh:
base/loader/elf_object.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
kern/linux/linux.hh:
kern/tru64/tru64.hh:
mem/packet.hh:
mem/page_table.cc:
mem/page_table.hh:
mem/physical.cc:
mem/request.hh:
mem/translating_port.cc:
sim/process.hh:
sim/system.cc:
    Fixing merged changes.

--HG--
extra : convert_revision : 2e94f21009395db654880fcb94ec806b6f5772c3
2006-03-09 19:21:35 -05:00
Ron Dreslinski
7f114ca419 Many changes that make the new mem system compile. Now to convert the rest of the tree to use the new mem system.
mem/mem_object.hh:
    Create constrtor so it compiles
mem/packet.hh:
    Fix typedefs so they compile, add in a few more headers for compilation
mem/page_table.cc:
    convert to new mem system so it compiles
mem/page_table.hh:
    fix it to the version that had asid support.  Make it compile in the new system
mem/physical.cc:
    Fix some compilation bugs
mem/physical.hh:
    Add a type that made compile fail
mem/port.hh:
    Fix a spelling error that messed up compilation
mem/request.hh:
    fix typedefs and forward declerations so it compiles

--HG--
extra : convert_revision : 580fb1ba31ada799ff0122601b8b5a8d994bb8af
2006-02-15 14:21:09 -05:00
Ron Dreslinski
eabb0cfc78 Pushing current state. Need to fix compilation problems, have moved the SCONS script to build memory objects first.
Some places I could have been using a forward decleration and that should be cleaned up as well.

SConscript:
    Changed to move new memory object compilation to the top.  See the errors right away.
    Will also need to update all other objects that included the old memory system to use the new one.  But not until we at least get the mem system compiling first.
mem/packet.hh:
    Adding includes and typedefs to fix compilation errors
mem/request.hh:
    Add definition for compilation issues

--HG--
extra : convert_revision : 34d9ae534a7a625445b981e81c7a1f856517cb04
2006-02-07 17:33:03 -05:00
Ron Dreslinski
c0f012d13d Listing some of the enum structures
--HG--
extra : convert_revision : d6ba1873826ee017bf2e4975a44eb2494a323132
2006-01-31 14:09:43 -05:00
Ron Dreslinski
a1033448ea Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point.
mem/bus.hh:
    Inital crack at a bus object that has ports.  Still need to clean up the include file issues.
mem/mem_object.hh:
    Decleration of a base memory object.  Derives from simobject and adds a function to get the port associated with the object.
mem/packet.hh:
    Inital crack at the packet decleration.  Still need to clean up the include file issues.
mem/port.hh:
    Inital crack at the port decleration.  Still need to clean up the include file issues.
mem/request.hh:
    Inital crack at the request decleration.  Still need to clean up the include file issues.

--HG--
extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
2006-01-31 12:12:49 -05:00