Commit graph

7 commits

Author SHA1 Message Date
Ali Saidi
ac36fb6e64 add fsr to the list of registers we are interested in
--HG--
extra : convert_revision : 2cc0d0144abab264aa0ec8c07242cdab2dffd4f8
2007-01-30 18:27:04 -05:00
Ali Saidi
2939d7d061 Make Sparc traceflag even more chatty
some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct

src/arch/sparc/floatregfile.cc:
    Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
    add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
    some fixes to fp instructions to use the single precision registers
    fix smul again
    fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
    if this is an fp op emit fp check code
src/cpu/exetrace.cc:
    check fp regs as well as int regs
src/cpu/m5legion_interface.h:
    add fpregs to m5legion struct

--HG--
extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
2007-01-26 18:57:16 -05:00
Ali Saidi
ff88f3b13a Compare legion and m5 tlbs for differences
Only print faults instructions that aren't traps or faulting loads

src/cpu/exetrace.cc:
    Compare the legion and m5 tlbs and printout any differences
    Only show differences if the instruction isn't a trap and isn't a memory
    operation that changes the trap level (a fault)
src/cpu/m5legion_interface.h:
    update the m5<->legion interface to add tlb data

--HG--
extra : convert_revision : 6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
2006-12-27 14:35:23 -05:00
Ali Saidi
92c5a5c8cb More changes to get SPARC fs closer. Now at 1.2M cycles before difference
configs/common/FSConfig.py:
    seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
    change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
    For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
    Use instruction count from cpu rather than cycles because that is what legion does
    we can change it back after were done with legion
src/base/bitfield.hh:
    add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
    add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
    compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
    change asserts of packet success to if panics wrapped with NDEBUG defines
    so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
    expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
    convert some tabs to spaces
src/python/m5/objects/T1000.py:
    add more fake devices for each l1 bank and each memory controller

--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
2006-12-04 00:54:40 -05:00
Ali Saidi
aa19b2e7bc fix endian issues with condition codes
use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?

src/arch/sparc/faults.cc:
    set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
    fix endian issues with condition codes
src/arch/sparc/tlb.hh:
    add implemented physical addres constants
src/arch/sparc/utility.hh:
    add tlb.hh to utilities
src/base/loader/raw_object.cc:
    add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
    use memcpy instead of bcopy
src/cpu/exetrace.cc:
    clean up printing a bit more
src/cpu/m5legion_interface.h:
    add tons to the shared interface
src/dev/ethertap.cc:
    s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
    fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
    hack to make sure htole() works...

--HG--
extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
2006-11-10 20:17:42 -05:00
Ali Saidi
cb172d0332 Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.

SConstruct:
    Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
    add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
    add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
    add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
    add option to try raw when nothing works
src/cpu/exetrace.cc:
    cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
    change the instruction to be 32 bits because it is
src/mem/physical.cc:
    fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
    Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
    Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
    add the ability to add Addr() together

--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
2006-11-09 18:22:46 -05:00
Ali Saidi
f7a35c33d7 add code to operate in lockstep with legion
src/python/m5/main.py:
    add option to operate in lockstep with legion

--HG--
extra : convert_revision : 2cc90ec0cf7e8d028ee813c2034a77415671a628
2006-11-07 15:51:37 -05:00