Lisa Hsu
c55a467a06
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
...
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
2008-11-02 21:56:57 -05:00
Ali Saidi
f4bceb9760
Libelf: Append options to CCFLAGS for warning free libelf compile instead of deleting CCFLAGS. Should fix 64bit OS X compile problem.
2008-10-28 21:13:21 -04:00
Clint Smullen
95af120e60
CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU.
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The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.
Signed-off By: Ali Saidi
2008-10-27 18:18:04 -04:00
Clint Smullen
cfa32d8de7
Checkpointing: createCountedDrain function, it was only returning an Event, which does not expose a setCount method to Python.
...
Signed-off By: Ali Saidi
2008-10-27 19:46:01 -04:00
Ali Saidi
aadae0b06e
BATCH: Run as, ar, and ranlib with BATCH_CMD so that they execute on the batch hosts, not local host.
2008-10-26 14:45:47 -04:00
Lisa Hsu
8788d703f8
s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in
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comments.
2008-10-23 16:49:17 -04:00
Lisa Hsu
546a6c0c1b
probe function no longer used anywhere.
2008-10-23 16:49:13 -04:00
Lisa Hsu
7a28ab2d18
remove the totally obsolete split cache
2008-10-23 16:11:28 -04:00
Nathan Binkert
9836d81c2b
style: Use the correct m5 style for things relating to interrupts.
2008-10-21 07:12:53 -07:00
Ali Saidi
aac93b7d0c
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-20 19:00:07 -04:00
Ali Saidi
b760b99f4d
O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
...
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.
Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.
Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
2008-10-20 16:22:59 -04:00
Lisa Hsu
4fac54f227
Automated merge with ssh://daystrom.m5sim.org//z/repo/m5
2008-10-19 22:50:53 -04:00
Nathan Binkert
9b8011e255
need to add packet_access.hh in order to get tempalte definition
2008-10-16 22:22:47 -07:00
Nathan Binkert
81f5da1e89
get rid of local variable that's only used in an assert so fast compiles
2008-10-16 22:22:17 -07:00
Lisa Hsu
101c2d9174
Automated merge with ssh://daystrom.m5sim.org//z/repo/m5
2008-10-16 14:16:26 -04:00
Lisa Hsu
90e40ca982
This function declaration isn't used anywhere.
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HG: user: Lisa Hsu <hsul@eecs.umich.edu> HG: branch default HG: changed
src/mem/cache/cache.hh
2008-10-14 17:22:03 -04:00
Nathan Binkert
5b07448cf1
eventq: make python events actually work
2008-10-14 09:34:11 -07:00
Nathan Binkert
ff2eea1ba3
eventq: revert code for unserializing events.
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Since I never implemented a proper solution, put it back to something that
at least works for now. Once I add more event queues, I'll have to really
fix this though
2008-10-14 09:33:52 -07:00
Gabe Black
809f6cb6d1
CPU: Explain why some code is commented out.
2008-10-12 23:52:02 -07:00
Gabe Black
34ca72d16d
Get rid of some commented out code.
2008-10-12 23:50:22 -07:00
Gabe Black
3c4567f2a6
X86: Set the delayed commit flag in x86 microops appropriately.
2008-10-12 23:29:10 -07:00
Gabe Black
33ebd04474
X86: Make the local APIC timer event generate an interrupt.
2008-10-12 23:28:49 -07:00
Gabe Black
bdc28d793d
X86: Implement the EOI register in the local APIC.
2008-10-12 23:28:11 -07:00
Gabe Black
fd37688294
X86: Add some DPRINTFs to the local APIC.
2008-10-12 23:27:45 -07:00
Gabe Black
be6055e0f2
X86: Make auto eoi mode work in the I8259 PIC.
2008-10-12 23:27:08 -07:00
Gabe Black
fb5bb434a9
X86: Make non-specific EOI commands work.
2008-10-12 23:25:48 -07:00
Gabe Black
8e664f3959
X86: Make the I8259 PIC accept a specific EOI command.
2008-10-12 23:22:58 -07:00
Gabe Black
e3004c579f
X86: Fix the segment setting code in IRET, and make it restore the flags.
2008-10-12 23:05:22 -07:00
Gabe Black
349a155b6e
X86: Panic when an unimplemented fault is invoked, rather than spinning forever
2008-10-12 23:00:28 -07:00
Gabe Black
564eda827b
X86: Implement the swapgs instruction.
2008-10-12 23:00:07 -07:00
Gabe Black
a2e0d539d8
X86: Add wrval/rdval microops for reading significant miscregs.
2008-10-12 22:55:55 -07:00
Gabe Black
9e8e2f9ec6
X86: Make the x86 interrupt fault kick off the interrupt microcode.
2008-10-12 22:42:10 -07:00
Gabe Black
4c19c56a77
X86: Implement entering an interrupt in microcode.
2008-10-12 22:42:03 -07:00
Gabe Black
f813a4be49
X86: Make sure register microops set fault rather than returning one.
2008-10-12 22:24:06 -07:00
Gabe Black
961b40cdb5
X86: Implement an wrdh microop which loads bases/offsets from 16 byte descriptors.
2008-10-12 22:16:53 -07:00
Gabe Black
989fa4fc0f
X86: Make the MicroPC type 16 bit.
2008-10-12 20:48:24 -07:00
Gabe Black
6074b1abf2
X86: Implement local labels for the ROM that actually refer into the ROM.
2008-10-12 20:44:11 -07:00
Gabe Black
6b46e5204d
X86: Implement the chks check of interrupt gate target code segments.
2008-10-12 20:38:22 -07:00
Gabe Black
30feb90c1c
X86: Add a check type for interrupt gates.
2008-10-12 20:33:37 -07:00
Gabe Black
15f5bb3055
X86: Fix chks checking the submode for stack segments.
2008-10-12 20:29:52 -07:00
Gabe Black
9e1fe2050a
X86: Let segment manipulation microops be conditional.
2008-10-12 20:25:06 -07:00
Gabe Black
e9158d763a
X86: Let the microassembler know about the microcode only H segment.
2008-10-12 20:17:38 -07:00
Gabe Black
223fc41c07
X86: Fix the rdbase microop
2008-10-12 20:07:46 -07:00
Gabe Black
0756dbb37a
X86: Don't fetch in the simple CPU if you're in the ROM.
2008-10-12 19:32:06 -07:00
Gabe Black
f245358343
Get rid of old RegContext code.
2008-10-12 17:57:46 -07:00
Gabe Black
cefb768131
X86: Create a handy way to access labels from the ROM in microcode.
2008-10-12 17:52:51 -07:00
Gabe Black
e5f8092467
X86: Make X86's microcode ROM actually do something.
2008-10-12 17:48:44 -07:00
Gabe Black
c9ea0b7349
CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM.
2008-10-12 16:59:55 -07:00
Gabe Black
2736086d7c
CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
2008-10-12 15:59:21 -07:00
Gabe Black
6fd4eff68f
X86: Create an eret microop which returns from ROM to combinational decoding.
2008-10-12 15:53:04 -07:00
