Commit graph

18 commits

Author SHA1 Message Date
Jason Power
670f44e05e Ruby: Update backing store option to propagate through to all RubyPorts
Previously, the user would have to manually set access_backing_store=True
on all RubyPorts (Sequencers) in the config files.
Now, instead there is one global option that each RubyPort checks on
initialization.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-02-26 09:58:26 -06:00
Nilay Vaish
0811f21f67 ruby: provide a backing store
Ruby's functional accesses are not guaranteed to succeed as of now.  While
this is not a problem for the protocols that are currently in the mainline
repo, it seems that coherence protocols for gpus rely on a backing store to
supply the correct data.  The aim of this patch is to make this backing store
configurable i.e. it comes into play only when a particular option:
--access-backing-store is invoked.

The backing store has been there since M5 and GEMS were integrated.  The only
difference is that earlier the system used to maintain the backing store and
ruby's copy was write-only.  Sometime last year, we moved to data being
supplied supplied by ruby in SE mode simulations.  And now we have patches on
the reviewboard, which remove ruby's copy of memory altogether and rely
completely on the system's memory to supply data.  This patch adds back a
SimpleMemory member to RubySystem.  This member is used only if the option:
access-backing-store is set to true.  By default, the memory would not be
accessed.
2014-11-06 05:42:21 -06:00
Nilay Vaish
3022d463fb ruby: interface with classic memory controller
This patch is the final in the series.  The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system.  This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs.  Classic's memory controller is more up to date and
supports multiple different types of DRAM.  This also brings classic and
ruby ever more close.  The patch also changes ruby's memory controller to
expose the same interface.
2014-11-06 05:42:21 -06:00
Nilay Vaish
407f37e15f ruby: move all statistics to stats.txt, eliminate ruby.stats 2014-01-10 16:19:47 -06:00
Akash Bagdia
7eccb1b779 config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.
2013-06-27 05:49:49 -04:00
Nilay Vaish
221d39284e ruby: convert block size, memory size to unsigned 2013-02-10 21:43:07 -06:00
Andreas Sandberg
c0ab52799c sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
2012-11-02 11:32:01 -05:00
Nilay Vaish
c5bf1390aa Ruby System: Convert to Clocked Object
This patch moves Ruby System from being a SimObject to recently introduced
ClockedObject.
2012-09-10 12:21:01 -05:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
c86f849d5a Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
2011-06-30 19:49:26 -05:00
Nathan Binkert
bd18ac8287 ruby: get rid of ruby's Debug.hh
Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace
2011-01-10 11:11:20 -08:00
Brad Beckmann
8b15ed7ebf ruby: Added flag to disable mem_vec allocation
The RubySystem flag no_mem_vec will disable Ruby from allocating it's memory
data array.
2010-03-21 21:22:21 -07:00
Brad Beckmann
d464087101 ruby: Added copyright to many Ruby *.py files 2010-03-21 21:22:20 -07:00
Brad Beckmann
134cc3d48d ruby: convert to M5 MemorySize
Converted both ruby caches and directory memory to use the M5 MemorySize python
type.
2010-01-29 20:29:23 -08:00
Brad Beckmann
1907e39fd2 ruby: added ruby stats print
Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.
2010-01-29 20:29:21 -08:00
Brad Beckmann
63a60cc81e ruby: Removed the tech_nm variable from RubySystem 2010-01-29 20:29:19 -08:00
Brad Beckmann
12daaed84a ruby: Added clock to ruby system
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
2010-01-29 20:29:19 -08:00
Steve Reinhardt
a8ea70dac6 ruby: Calculate system total memory capacity in Python
rather than in RubySystem object.
2010-01-29 20:29:18 -08:00
Steve Reinhardt
98c94cfe3c ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
2010-01-29 20:29:17 -08:00