Commit graph

15 commits

Author SHA1 Message Date
Brad Beckmann
92cfd1cac7 ruby: Ruby support for sparse memory
The patch includes direct support for the MI example protocol.
2010-03-21 21:22:21 -07:00
Nathan Binkert
0bbf63f17a slicc: Change the code generation so that the generated code is easier to read 2010-03-12 18:42:56 -08:00
Nathan Binkert
140785d24c ruby: get rid of std-includes.hh
Do not use "using namespace std;" in headers
Include header files as needed
2010-03-10 18:33:11 -08:00
Nathan Binkert
cf86532857 slicc: have a central mechanism for creating a code_formatter.
This makes it easier to add global variables like protocol
2010-03-10 16:22:26 -08:00
Brad Beckmann
a407675106 ruby: Fixed slicc to initialize the m_is_blocking flag 2010-02-10 16:40:54 -08:00
Brad Beckmann
3a835c7cbb ruby: Added Cache and MemCntrl profiler calls 2010-01-29 20:29:23 -08:00
Brad Beckmann
2a0555470c ruby: Converted MOESI_hammer dma cntrl to new config system 2010-01-29 20:29:19 -08:00
Brad Beckmann
ed81489954 ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system.  Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects.  This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
42bebab779 ruby: connects sm queues to the network 2010-01-29 20:29:18 -08:00
Steve Reinhardt
c6f1d959be ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
2010-01-29 20:29:17 -08:00
Derek Hower
07ea0891f1 ruby: new atomics implementation
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
2010-01-19 17:11:36 -06:00
Derek Hower
279f179bab merge 2010-01-19 15:48:12 -06:00
Brad Beckmann
20f872ed2a ruby: Added boolean to State Machine parameters
* * *
ruby: Removed primitive .hh includes
2009-11-18 16:34:32 -08:00
Brad Beckmann
994169327a ruby: slicc action error fix
Small fix to the State Machine error message when duplicate actions are defined.
2009-11-18 13:55:58 -08:00
Nathan Binkert
2278363015 slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code.  The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
2009-09-22 18:12:39 -07:00