Commit graph

8 commits

Author SHA1 Message Date
Ali Saidi
c27c122afc Add the bus and connector objects to scons
change getPort parameter from char* to string
Add an extra phase between construction and init called connect

SConscript:
    Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    the connection to memory shouldn't be made until we know the memory
    object exists (e.g. after construction)
dev/io_device.hh:
    change to const string
mem/bus.hh:
    change getPort parameter from char* to string
    initialize num_interfaces
mem/mem_object.hh:
    change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
    change getPort parameter from char* to string
    get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
    get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
    Add an extra phase between construction and init called connect

--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
2006-03-26 21:44:22 -05:00
Ali Saidi
b38f67d5b7 Implement a very very simple bus
requestTime -> time
responseTime -> packet.time

Make CPU and memory able to connect to the bus

dev/io_device.cc:
    update for request and packet both having a time
    hand platform off to port for eventual selection of request modes
dev/io_device.hh:
    update for request and packet both havig a time
    hand platform off to port for eventual selection of request modes
mem/bus.hh:
    Add a device map struct that maps a range to a portId
    - Which needs work it theory it should be an interval tree
    - but it is a list and works fine right now

    Add a function called findPort which returns port for an addr range

    Add a deviceBlockSize function that really shouldn't exist, but it
    was easier than fixing the translating port
mem/packet.hh:
    add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
    Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
    remove requestTime/responseTime for just time in request which
    is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
    Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
    Fix for new bus object

--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
2006-03-25 18:31:20 -05:00
Steve Reinhardt
944646124e Rename Port address range functions... like the block size
functions, the send/recv*Query naming seems awkward.
Also create a typedef for AddrRangeList.

--HG--
extra : convert_revision : dd0ff3fad06ec329c82c199700d0a6264f1271d3
2006-02-21 12:32:45 -05:00
Ron Dreslinski
2f644efafa Fixed some void functions with returns, first stab at cpu ports.
cpu/simple/cpu.hh:
    Adding port definitions to simple cpu, still needs work.
mem/bus.hh:
    no return for void functions

--HG--
extra : convert_revision : 42e5bc16af187d3a46eb25a15b600a8a11b88cc5
2006-01-31 14:39:41 -05:00
Ali Saidi
fccd113e2f Merge zizzer:/bk/newmem
into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 3eb1a665cb813df974aa2815a794b459473c0a77
2006-01-31 14:20:48 -05:00
Ali Saidi
4875b33467 changed sendresult -> bool,tick,void as appropriate
first crack at io devices code
made CpuRequest that derives from Request

dev/io_device.cc:
dev/io_device.hh:
    first crack at the classes for Pio and Dma devices
dev/platform.hh:
    We are going to a system pointer to get info about the memory system
mem/bus.hh:
    changed sendresult -> bool,tick,void as appropriate
mem/port.hh:
    changed sendresult -> bool,tick,void as appropriate;
    removed the sendTiming(pkt,t) call since it is not really
    implementable in a generic fashion
mem/request.hh:
    pulled items from Request into CpuRequest

--HG--
extra : convert_revision : 6213cf2b66417fa023b80884d9e623e78f5aa891
2006-01-31 14:20:39 -05:00
Ron Dreslinski
95088d141f Add proper includes
--HG--
extra : convert_revision : c5f909d00b6025cd8f14544f7e2c9c50610c0cd3
2006-01-31 14:15:33 -05:00
Ron Dreslinski
a1033448ea Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point.
mem/bus.hh:
    Inital crack at a bus object that has ports.  Still need to clean up the include file issues.
mem/mem_object.hh:
    Decleration of a base memory object.  Derives from simobject and adds a function to get the port associated with the object.
mem/packet.hh:
    Inital crack at the packet decleration.  Still need to clean up the include file issues.
mem/port.hh:
    Inital crack at the port decleration.  Still need to clean up the include file issues.
mem/request.hh:
    Inital crack at the request decleration.  Still need to clean up the include file issues.

--HG--
extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
2006-01-31 12:12:49 -05:00