src/mem/cache/cache_impl.hh:
When upgrades change to readEx make sure to allocate the block
Fix dprintf
--HG--
extra : convert_revision : 8700a7e47ad042c8708302620b907849c4bfdded
src/mem/cache/base_cache.cc:
On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag.
src/mem/packet.cc:
src/mem/packet.hh:
Create a wrapper to toggle the hasData flag on delayed responses
--HG--
extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
Working on that now.
src/mem/cache/base_cache.cc:
Keep a list of the responders so we can search them on functional accesses.
src/mem/cache/base_cache.hh:
Properly put things on a list for responses so we can search the list.
Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there)
src/mem/cache/cache_impl.hh:
Properly return when the first read hit on a functional access.
Make sure to call to check the other ports list of packets before forwarding it out.
--HG--
extra : convert_revision : 1d21cb55ff29c15716617efc48441329707c088a
src/mem/packet.cc:
Make sure to copy the whole data (we were one byte short)
src/mem/tport.cc:
Fix for the proper semantics of fixPacket
--HG--
extra : convert_revision : 215e05db9099d427afd4994f5b29079354c847d8
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
files so the directories can easily be deleted.
Remove the FullCPU from the ALL_CPU_LIST and only add it if
it exists.
--HG--
extra : convert_revision : b16f56bb92a0063803c5099732dc289fe4363768
align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris
src/SConscript:
DWARF2 symbol support seems to be broken on Solaris. Use stabs+
src/base/statistics.hh:
align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris
--HG--
extra : convert_revision : bc875a4fdfb4553062d3278537bc32a5ab9b6cca
configs/common/Simulation.py:
simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
make a new m5 param called MaxTick.
src/sim/host.hh:
fix the M5 def. of MaxTick
src/sim/main.cc:
Simplify the MaxTick/num_cycles parsing within main.cc
--HG--
extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
src/python/m5/objects/BaseCPU.py:
These parameters should have been removed in an earlier push.
--HG--
extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/arch/sparc/faults.hh:
Hand merged.
--HG--
extra : convert_revision : 1bcefe47fa98e878a0dfbcfa5869b5b171927911
