don't regenerate address from block in cache so that tags can
turn around and use address to look up block again.
--HG--
extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).
--HG--
extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
Fix a small writeback bug when missing in the L2 in atomic mode
src/mem/bus.cc:
Fix a comment to make sense
src/mem/cache/cache_impl.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
Also fix a small writeback miss in L2 issue
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Do a functional access to levels above on a read as a temporary solution for L2's in FS
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
Update ref's for writeback changes
--HG--
extra : convert_revision : 937febd577b16b7fd97a5a68acaf53541828a251
Fixes for Mem Leak associated with Writebacks.
src/mem/cache/miss/mshr_queue.cc:
Fixes for Mem Leak associated with Writebacks. (Double Delete removed)
--HG--
extra : convert_revision : 7a52ddd57da35995896f2c4438a58aa53f762416
src/mem/cache/cache_impl.hh:
When upgrades change to readEx make sure to allocate the block
Fix dprintf
--HG--
extra : convert_revision : 8700a7e47ad042c8708302620b907849c4bfdded
Working on that now.
src/mem/cache/base_cache.cc:
Keep a list of the responders so we can search them on functional accesses.
src/mem/cache/base_cache.hh:
Properly put things on a list for responses so we can search the list.
Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there)
src/mem/cache/cache_impl.hh:
Properly return when the first read hit on a functional access.
Make sure to call to check the other ports list of packets before forwarding it out.
--HG--
extra : convert_revision : 1d21cb55ff29c15716617efc48441329707c088a
not necessarily 100% there yet.
src/mem/cache/cache_impl.hh:
Generate response packet on failed store conditional.
src/mem/packet.hh:
Clear packet flags when reinitializing.
(SATISFIED in particular is one we don't want to leave set.)
--HG--
extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
src/cpu/memtest/memtest.cc:
Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
Fix cache to handle functional accesses properly based on memtester changes
Still need to fix functional accesses in timing mode now that the memtester can test it.
--HG--
extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
?? doesn't compile in warn statements
Should have been false, where I had a true.
src/cpu/o3/lsq_impl.hh:
Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
Forgot to signal atomic mode in snoopProbe
--HG--
extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
Now to try L2 caches in FS.
src/mem/cache/base_cache.hh:
Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Properly forward invalidates in atomic/timing uni-coherence
--HG--
extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7
src/mem/cache/cache_impl.hh:
Get the read data from the highest level of cache on a functional access
--HG--
extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
--HG--
extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
Still need to fix upgrades to use this path
src/mem/cache/base_cache.cc:
Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
Use copy of packet, because sendTiming may have changed the pkt
Also, delete the copy when the time comes
--HG--
extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)
Now both timing/atomic caches with MOESI in UP fail at same point.
src/dev/io_device.hh:
DMA's should send WriteInvalidates
src/mem/bridge.cc:
Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Fix CSHR's for flow control.
src/mem/packet.hh:
Make a writeInvalidateResp, since the DMA expects responses to it's writes
--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
src/mem/cache/base_cache.hh:
Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
Remove top level parameters from the cache
--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses
--HG--
extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
Update retry mechanism
src/mem/cache/base_cache.cc:
Rework the retry mechanism
src/mem/cache/base_cache.hh:
Rework the retry mechanism
Try to fix memory bug
src/mem/cache/cache_impl.hh:
Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
Fix mem leak on writebacks
--HG--
extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
src/mem/cache/base_cache.cc:
Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
Fix a bug with the blocking code
src/mem/cache/cache.hh:
AFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
Fix a bug with snoop hits in WB buffer
Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
More interesting testcase
--HG--
extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
Not fully implemented yet, but good enough for single level cache coherence
src/mem/packet.hh:
Add a bit to distinguish invalidates and upgrades
--HG--
extra : convert_revision : 5bf50d535857cea37fbdaf7993915d1332cb757e
Remove some dead code.
src/mem/cache/cache_impl.hh:
Upgrades don't need a response.
Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
Upgrades don't require a response
--HG--
extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
src/cpu/memtest/memtest.cc:
Fix functional return path
src/cpu/memtest/memtest.hh:
Add snoop ranges in
src/mem/cache/base_cache.cc:
Properly signal NACKED
src/mem/cache/cache_impl.hh:
Catch nacked packet and panic for now
--HG--
extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
src/mem/cache/cache_impl.hh:
Add more usefull DPRINTF's
REmove the PC to get rid of asserts
--HG--
extra : convert_revision : 3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.hh:
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
--HG--
extra : convert_revision : 2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
src/mem/cache/cache_impl.hh:
Fix a error case by putting a panic in.
Make sure to propogate sendFunctional calls with functional not atomic.
--HG--
extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
src/mem/cache/cache_impl.hh:
Make sure to pop the list. Fixes infinite writeback bug.
src/mem/cache/miss/mshr_queue.cc:
Add an assert as sanity check in case .full() stops working again.
--HG--
extra : convert_revision : d847e49a397eeb0b7c5ac060fcfc3eaeac921311
