at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early.
--HG--
extra : convert_revision : f237363eababb2aad67e5b41670cf40be048a042
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.cc:
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
correct protection defines
src/arch/sparc/ua2005.cc:
set the softint appropriately on an timer compare interrupt
--HG--
extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
turn warnings into dprintfs
src/arch/sparc/miscregfile.cc:
turn dprintfn into dprintfs
--HG--
extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit
--HG--
extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
src/cpu/o3/commit_impl.hh:
Oops, changed the logic a little bit. Fix it up to how it used to be.
--HG--
extra : convert_revision : df7f69b0997207b611374c3c92880f3a405e88be
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48
src/arch/sparc/tlb.cc:
Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
itb should be 64 entries too
--HG--
extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
Only print faults instructions that aren't traps or faulting loads
src/cpu/exetrace.cc:
Compare the legion and m5 tlbs and printout any differences
Only show differences if the instruction isn't a trap and isn't a memory
operation that changes the trap level (a fault)
src/cpu/m5legion_interface.h:
update the m5<->legion interface to add tlb data
--HG--
extra : convert_revision : 6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
m5.internal.event.create(). It takes a python object and a
Tick and calls process() when the Tick occurs.
--HG--
extra : convert_revision : 5e4c9728982b206163ff51e6850a1497d85ad7a3
src/python/swig/init.cc so that it's not as easy to forget
about it when you add a new swig module.
--HG--
extra : convert_revision : 5cc4ec0838e636aa761901effb8986de58d23e03
Also don't call (*activeThreads).end() over and over. Just
call activeThreads->end() once and save the result.
Make sure we always check that there are elements in the list
before we grab the first one.
--HG--
extra : convert_revision : d769d8ed52da99532d57a9bbc93e92ddf22b7e58
bugfixes and demap implementation in tlb
ignore some more differencs for one cycle
src/arch/sparc/isa/formats/mem/blockmem.isa:
twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
fix the fault check for twinx
src/arch/sparc/tlb.cc:
tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
don't halt on a couple more instruction (ldx, stx) when things differ
beacuse of the way tlb faults are handled in legion.
--HG--
extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71
don't regenerate address from block in cache so that tags can
turn around and use address to look up block again.
--HG--
extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
Make the TLB ok to translate QUAD_LDD
src/arch/sparc/isa/decoder.isa:
move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
Make QUAD_LDD asi ok to execute
--HG--
extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
m5 style and fixing whitespace. For whitespace, any tabs in
leading whitespace on a line are converted to spaces, and any
trailing whitespace is removed.
--HG--
extra : convert_revision : d0591663c028a388635fc71c6c1d31f700748cf6
src/arch/sparc/isa/decoder.isa:
Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.
--HG--
extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
src/arch/sparc/isa/decoder.isa:
Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
Comment explaining twin load operands.
--HG--
extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.
src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
pioSize indicates SIZE, not a mask
--HG--
extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948
