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Author SHA1 Message Date
Korey Sewell 34715cc691 Fix offset in removeThread() function so that float registers start freeing up 
from the right point (#32 usually) instead of restarting at 0 and double-freeing.

Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.

--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
 2008-02-27 16:48:33 -05:00
Steve Reinhardt e6d6adc731 Revamp cache timing access mshr check to make stats sane again. 
--HG--
extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
 2008-02-26 22:03:28 -08:00
Rick Strong fcfc8b8c4f Configs: Make using Simpoints easier with some config files that support them easily 
--HG--
extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd
 2008-02-27 00:35:09 -05:00
Gabe Black 43ecce5fda X86: Put in initial implementation of the local APIC. 
--HG--
extra : convert_revision : 1708a93d96b819e64ed456c75dbb5325ac8114a8
 2008-02-26 23:39:53 -05:00
Gabe Black 98d2ca403e X86: Implement the INVLPG instruction and the TIA microop. 
--HG--
extra : convert_revision : 31db1ee082f6c3ca5443cba1eb335e408661ead2
 2008-02-26 23:39:22 -05:00
Gabe Black 8b4796a367 TLB: Make a TLB base class and put a virtual demapPage function in it. 
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
 2008-02-26 23:38:51 -05:00
Gabe Black 7bde0285e5 X86: Get PCI config space to work, and adjust address space prefix numbering scheme. 
--HG--
extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
 2008-02-26 23:38:01 -05:00
Steve Reinhardt bdf3323915 Cache: better comments particularly regarding writeback situation. 
--HG--
extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
 2008-02-26 20:17:26 -08:00
Gabe Black ec1a4cbbc7 Bus: Fix the bus timing to be more realistic. 
--HG--
extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc
 2008-02-26 02:20:08 -05:00
Steve Reinhardt 4597a71cef Make L2+ caches allocate new block for writeback misses 
instead of forwarding down the line.

--HG--
extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
 2008-02-16 14:58:03 -05:00
Ali Saidi 9faec83ac5 CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults. 
--HG--
extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
 2008-02-14 16:14:35 -05:00
Ali Saidi a33a3f7c55 Update copyright dates 
--HG--
extra : convert_revision : 547e7ddff6b8005a9eaad60970bc51984e84fcd1
 2008-02-11 12:35:28 -05:00
Steve Reinhardt 71835d42df Automated merge with file:/home/stever/hg/m5-orig 
--HG--
extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d
 2008-02-11 08:31:26 -08:00
Steve Reinhardt 2f7421b12b EXTRAS now points to src instead of needing 'src' subdir. 
--HG--
extra : convert_revision : 8e7e4516ace8c7852eeea3c479bfd567839a8061
 2008-02-11 08:04:01 -08:00
Nicolas Zea 4c7eb21119 Bus: Only update port cache when there is an item to update it with. 
--HG--
extra : convert_revision : 84848fd48bb9e6693a0518c862364142b1969aa8
 2008-02-10 19:41:03 -05:00
Ali Saidi d167e2bb97 IGbE: Fix a couple of bugs. 
--HG--
extra : convert_revision : a1f16bd82b6fbd5b6b5dc0f08b9e69858bea86ca
 2008-02-10 19:32:12 -05:00
Steve Reinhardt 9d7a69c582 Fix #include lines for renamed cache files. 
--HG--
extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
 2008-02-10 14:45:25 -08:00
Steve Reinhardt d56e77c180 Rename cache files for brevity and consistency with rest of tree. 
--HG--
rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc
rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh
rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc
rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh
rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc
rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc
rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh
rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc
rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh
rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc
rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh
rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc
rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh
rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc
rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh
rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc
rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh
rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc
rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh
rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py
rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc
rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh
rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh
extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62
 2008-02-10 14:15:42 -08:00
Stephen Hines 6cc1573923 Make the Event::description() a const function 
--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
 2008-02-06 16:32:40 -05:00
Stephen Hines 0ccf9a2c37 Add base ARM code to M5 
--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
 2008-02-05 23:44:13 -05:00
Steve Reinhardt b96631e1a0 Cleaned up os.path imports a bit. 
--HG--
extra : convert_revision : ee75bf9abd249ab053e804739cc50972475cd5b6
 2008-02-05 17:43:45 -08:00
Steve Reinhardt d725ff450d Make EXTRAS work for SConsopts too. 
Requires pushing source files down into 'src' subdir relative
to directory listed in EXTRAS.

--HG--
extra : convert_revision : ca04adc3e24c60bd3e7b63ca5770b31333d76729
 2008-02-05 17:40:08 -08:00
Gabe Black ca313e2303 X86: Put an SMBios/DMI table in memory. 
This is basically just the header right now, but there's an untested
mechanism in place to fill out the table and make sure everything is
updated correctly.

--HG--
extra : convert_revision : c1610c0dfa211b7e0d091a04133695d84f500a1c
 2008-01-23 15:28:54 -05:00
Gabe Black 423bbe6499 X86: Optomize the bit scanning instruction microassembly a little. More can be done. 
--HG--
extra : convert_revision : 3cf6e972f0e41e3529a633ecbb31289e1bd17f0f
 2008-01-23 08:18:27 -05:00
Gabe Black 60c2d98fc0 X86: Implement and attach the BSR and BSF instructions. 
--HG--
extra : convert_revision : be7e11980092e5d1baff0e05d4ec910305966908
 2008-01-22 00:10:33 -05:00
Gabe Black f809637011 X86: Fill out group17 in the decoder. 
--HG--
extra : convert_revision : 66ab9c0fc3086f66e3d6d82d47964ecf406c3a8a
 2008-01-21 16:27:40 -05:00
Gabe Black 657b52fea1 X86: Use the existing boot_osflags instead of duplicating it. 
--HG--
extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a
 2008-01-21 04:32:34 -05:00
Ke Meng 0b6876a0c0 The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. 
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>

--HG--
extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
 2008-01-14 11:47:32 -05:00
Gabe Black c08b7802a9 X86: Redo the bit test instructions. 
--HG--
extra : convert_revision : 433c2a9f3675ed02f3be5ce759a440f2686d2ccd
 2008-01-12 06:41:32 -05:00
Gabe Black b705eba6e5 X86: Fix the wrmsr instruction. 
--HG--
extra : convert_revision : 12bc7e71226ebafb8eedadf6a3db82929e15e722
 2008-01-12 06:40:55 -05:00
Gabe Black 0ee67d4210 X86: Make the effective segment base shadow the regular one, not the selector. 
--HG--
extra : convert_revision : 498c7c16d664c784b196885b1f35c3c6386c9cfc
 2008-01-12 06:40:10 -05:00
Gabe Black 223e48e6ae X86: Make the IO ports work using extra physical address lines. Add a serial port. 
--HG--
extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
 2008-01-12 06:39:15 -05:00
Gabe Black 0e394fdfa4 X86: Fix the general IO instructions dataSize. 
--HG--
extra : convert_revision : 9774a52cb6a8e7632d1b1dc0706e5791cc18d238
 2008-01-12 06:37:35 -05:00
Geoffrey Blake f9c54d5a4b Temporary fix for ll/sc bug see flyspray task for more info: 
http://www.m5sim.org/flyspray/task/197

Signed-off by: Ali Saidi <saidi@eecs.umich.edu>

--HG--
extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81
 2008-01-06 00:19:45 -05:00
Steve Reinhardt 6c5a3ab8b2 Add ReadRespWithInvalidate to handle multi-level coherence situation 
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us.  We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A.  This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.

--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
 2008-01-02 15:22:38 -08:00
Steve Reinhardt bf9b3821bd Mark cache-to-cache MSHRs as downstreamPending when necessary. 
Don't mark upstream MSHR as pending if downstream MSHR is already in service.

--HG--
extra : convert_revision : e1c135ff00217291db58ce8a06ccde34c403d37f
 2008-01-02 15:18:33 -08:00
Steve Reinhardt 538da9e24d Don't DPRINTF in the middle of a PrintReq. 
--HG--
extra : convert_revision : 6358c014d14a19a34111c39827b05987507544bb
 2008-01-02 14:42:42 -08:00
Steve Reinhardt 87e5fd1755 Bug fix: functional cache port now needs otherPort set. 
--HG--
extra : convert_revision : fb007df73a77535a5dba19341f7b0b32e8c99548
 2008-01-02 14:42:24 -08:00
Steve Reinhardt cde5a79eab Additional comments and helper functions for PrintReq. 
--HG--
extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
 2008-01-02 13:46:22 -08:00
Steve Reinhardt 3952e41ab1 Add functional PrintReq command for memory-system debugging. 
--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
 2008-01-02 12:20:15 -08:00
Steve Reinhardt 659aef3eb8 Fix formatting and comments in cache_impl.hh 
--HG--
extra : convert_revision : 26d71cca5420ad03e16bf174e15dabe7f902da41
 2008-01-02 12:15:48 -08:00
Gabe Black 2cb7d4f068 SPARC: Fix a bug where the TLB would match against the wrong entries. 
--HG--
extra : convert_revision : 631b3b6a1416121b54bd9717ca1cdccdd5b8a1eb
 2008-01-01 18:20:08 -05:00
Ali Saidi 45ea1549c9 Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. 
--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
 2007-12-18 01:52:57 -05:00
Ali Saidi 71909a50de CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. 
--HG--
extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
 2007-12-16 03:48:13 -05:00
Gabe Black 27cc351688 X86: Please excuse my dear Aunt Sally. (precedence bug) 
--HG--
extra : convert_revision : 9ad4f31e7a962c3177896bcbfb93e2e54720d117
 2007-12-03 14:32:56 -08:00
Gabe Black 73caca57a8 X86: Make sure the memory index is calculated using the address size for bit test instructions. 
--HG--
extra : convert_revision : 9634675857dae53b5e79e49267c864a0265afde1
 2007-12-02 01:46:38 -08:00
Gabe Black b5d4018382 X86: Fix a copy/paste mistake where the bit test instructions were using an immediate where they should use a register. 
--HG--
extra : convert_revision : b0ee80e4c7fdb58a1eb85b3bcc82a0cdaa93330a
 2007-12-02 01:46:29 -08:00
Gabe Black 62ad1d2872 X86: Make the page not present panic more descriptive. 
--HG--
extra : convert_revision : 9360e47adb61e164ac218f2ea231eaa60bf3229d
 2007-12-02 01:46:14 -08:00
Gabe Black 82e705d713 X86: Start setting up the real mode data structure. 
--HG--
extra : convert_revision : ba6d4939d4d58da5586655c83f1617f47dc7e359
 2007-12-02 00:04:31 -08:00
Gabe Black 5de71e39d8 X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates. 
--HG--
extra : convert_revision : a702403de29772618abb5bd5c5555279d91bdd59
 2007-12-02 00:02:51 -08:00
Gabe Black 4c37f828f1 X86: Add in a missing "break". 
--HG--
extra : convert_revision : 2e48d8b0292bc3b78e4caa27dec20113d40e7d74
 2007-12-01 23:11:23 -08:00
Gabe Black 9805916cec X86: Actually do something for the MiscRegFile clear function. 
--HG--
extra : convert_revision : 36f8abaa9d09700d8ba9e09b4a10fa4dce580f36
 2007-12-01 23:10:42 -08:00
Gabe Black 42ae409746 X86: Move startup code to the system object to initialize a Linux system. 
--HG--
extra : convert_revision : a4796c79f41aa8b8f38bf2f628bee8f1b3af64be
 2007-12-01 23:09:56 -08:00
Gabe Black e7fc5c42f3 X86: Add a missing microcode file to the sconscript. 
--HG--
extra : convert_revision : 6da8a67e07bada169abf7f10aded8a90d4e63eae
 2007-12-01 23:07:41 -08:00
Gabe Black 67fee01026 X86: Fix a copy paste error in the bts microcode. 
--HG--
extra : convert_revision : c4ac007d35ac13211f9816f1104c84f2b447ddba
 2007-12-01 23:06:52 -08:00
Gabe Black 988c6f227a X86: Implement mov from control register. 
--HG--
extra : convert_revision : c8280f0686a3ae6d5c405327540ad15a3a5531f9
 2007-12-01 23:06:03 -08:00
Gabe Black fe833dd2c3 X86: First crack at far returns. This is grossly approximate. 
--HG--
extra : convert_revision : 23da0338af1f7663ae5ddf2289fb45dd32f37c42
 2007-12-01 23:05:01 -08:00
Gabe Black dc6f960171 X86: Reorganize segmentation and implement segment selector movs. 
--HG--
extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8
 2007-12-01 23:03:39 -08:00
Gabe Black a548067b01 X86: Make the "fault" microop predicated. 
--HG--
extra : convert_revision : ded34133afcd6af1f55b8991b82bad45258069d3
 2007-12-01 23:01:56 -08:00
Gabe Black 557bc80647 X86: Implement the LIDT instruction. 
--HG--
extra : convert_revision : 380515e985318311632e00b13000585afb052e3b
 2007-12-01 23:01:31 -08:00
Gabe Black 62c79ca637 X86: Implement the lgdt instruction. 
--HG--
extra : convert_revision : d1698a82df3c57cc9bbf8d5d190f271bfc7cb2e4
 2007-12-01 23:01:17 -08:00
Gabe Black 4e3ff42762 X86: Implement wrbase and wrlimit for loading pseudo descriptors. 
--HG--
extra : convert_revision : fe03c4aed95ef12773e80cdb3d9cff68a2b20f02
 2007-12-01 23:00:58 -08:00
Gabe Black bfc62d1a70 X86: Separate the effective seg base and the "hidden" seg base. 
--HG--
extra : convert_revision : 5fcb8d94dbab7a7d6fe797277a5856903c885ad4
 2007-12-01 23:00:15 -08:00
Gabe Black 7433032b39 SPARC: Fixes for invalidateAll and demapAll in the SPARC TLBs. 
--HG--
extra : convert_revision : 8de6c60b0e3e725eac11047a9d9888097dd359ff
 2007-11-30 16:49:27 -08:00
Gabe Black 38e804f7cd SPARC: Fix 32 bit register window flushing endian conversion. 
--HG--
extra : convert_revision : be91d6fecb44a85e983343704a098b456948af8a
 2007-11-29 20:20:18 -08:00
Gabe Black fa5e3b47c8 SPARC: Fix the initial stack to match what the Linux kernel does. 
--HG--
extra : convert_revision : a4451710d8463e52227fd8f760ab737ea8f404b5
 2007-11-29 00:00:26 -08:00
Gabe Black 16e99e4677 SPARC: Combine the 64 and 32 bit process initialization code. 
Alignment is done as it was for 32 bit processes.

--HG--
extra : convert_revision : 9368ad40dcc7911f8fc7ec1468c6a28aa92d196f
 2007-11-29 00:00:02 -08:00
Ali Saidi a84d9716d6 merge, no manual changes 
--HG--
extra : convert_revision : 6d6b744bbdfb09e7c3092368870a4f372241f9e8
 2007-11-29 00:23:14 -05:00
Rick Strong 376c7285ee Serialization: Fix serialization of file descriptors. Make sure open 
file descriptors are reopened and the file pointer is in the same
place as when the checkpoint occured.

Signed-off by: Ali Saidi

--HG--
extra : convert_revision : d9d2cd388c9c02f60e1269d6845891c35f94fc47
 2007-11-29 00:22:46 -05:00
Gabe Black 8a020d40d3 Make ports that aren't connected to anything fail more gracefully. 
--HG--
extra : convert_revision : 3803b28fb2fdfd729f01f1a44df2ae02ef83a2fc
 2007-11-28 14:39:19 -08:00
Gabe Black ab598eadbf imported patch pagewalker.patch 
--HG--
extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f
 2007-11-21 00:04:15 -08:00
Gabe Black ce26c3ccec Get rid of a file that should have never been committed. 
--HG--
extra : convert_revision : c0e678ce0ce0301bb3afff8bef4fcab7aef3c6fe
 2007-11-20 22:51:03 -08:00
Gabe Black e35c4f2f08 Merge with head. 
--HG--
extra : convert_revision : c4215e516c6d82ad466db898ffeefa0233ca110e
 2007-11-20 15:38:54 -08:00
Gabe Black a12d5975cc Simple CPU fix simple mistake in translateDataWriteAddr. 
--HG--
extra : convert_revision : 6a6a7d05f62d9d9868be0707e4dc186a5f7ecf7d
 2007-11-20 15:37:56 -08:00
Ali Saidi ac50694d1a Serialization: Serialize SPARC PTEs last so their nameOut() calls don't interfere with other serialization in the TLB. 
--HG--
extra : convert_revision : 8a8478a200cd3c65b2ac98944d1278454811d38f
 2007-11-19 22:47:08 -05:00
Ali Saidi 8026ecbb8e Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access. 
--HG--
extra : convert_revision : d6c3e93718991e7b68248242c80d8e6ac637ac51
 2007-11-19 18:23:43 -05:00
Steve Reinhardt 785eb13190 Make EXTRAS work for relative directories. 
Also print a little feedback when processing EXTRAS.

--HG--
extra : convert_revision : 9cb324b0d5bc60a3c98af6495f16415b529e4af2
 2007-11-16 20:10:33 -08:00
Steve Reinhardt 7d83cf35e1 Tweak check for writable block fill. 
--HG--
extra : convert_revision : c04281bcfc4cd23c7613aeccb21dc74452bcc951
 2007-11-16 20:10:33 -08:00
Steve Reinhardt f03a62008a Fix bug on exclusive response to ReadReq with pending WriteReq. 
--HG--
extra : convert_revision : 5429cd7ca84cf6348813a4607fa16f76aa5df7e0
 2007-11-16 20:10:32 -08:00
Korey Sewell 5d23f86e98 add back in clobbered MIPS fix for g++ 4.2 
--HG--
extra : convert_revision : 80ad1cc32c6e59925526abd274132e4f9e35f0c1
 2007-11-17 00:02:56 -05:00
Korey Sewell f2fea63c65 go back and fix up MIPS copyright headers 
--HG--
extra : convert_revision : 886e762e13b7a05d6d8a14bde6c2a3567c32a4d1
 2007-11-16 21:32:22 -05:00
Korey Sewell 52e6aa6284 move initCPU, processInterrupts declaration to core_specific file. 
--HG--
extra : convert_revision : 9bc88380f05f86c68117280f555c77eb4c627d7b
 2007-11-16 21:31:37 -05:00
Korey Sewell 92724490c9 Gabe's 32-bit X86 fix merge 
--HG--
extra : convert_revision : 6f79c5c785c93d6caef2ec26961b652cd51e30fe
 2007-11-16 19:16:01 -05:00
Gabe Black 7ffd88a54b X86: Fix 32 bit compilation. 
--HG--
extra : convert_revision : d16d68731a8480080ec6b8da3ebda8567e115a30
 2007-11-16 14:18:47 -08:00
Korey Sewell 923c385b97 remove unnecessary namespace 
--HG--
extra : convert_revision : 8936fe2246ca659a6dfe0835f66aa8232ed427de
 2007-11-15 20:52:59 -05:00
Korey Sewell d09ab2bd22 add thread id to misc. reg functions 
--HG--
extra : convert_revision : 35d073d1279947d943a0290832e09a5268dd0b76
 2007-11-15 20:35:49 -05:00
Korey Sewell 7c076479e4 add MicroPC functions back to thread context 
--HG--
extra : convert_revision : a9cfd2829c4aec191f5f9ec6ce7b5d1dccc92af1
 2007-11-15 20:35:31 -05:00
Korey Sewell cf9dc4b151 add microPC stuff back in. got deleted on changeset propragation somehow. 
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extra : convert_revision : 5e89484b2ef21457ffba35ef959df999a28c5676
 2007-11-15 19:48:53 -05:00
Korey Sewell 8f8e7fe08e put the flattenIndex stuff back in O3 AND put fatal() back in faults 
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extra : convert_revision : 16fb8d7f3fbc5f8f1fc3ed34427c3d90a3125ad0
 2007-11-15 16:38:09 -05:00
Korey Sewell 3110b157e6 fix MIPS headers 
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extra : convert_revision : 2870a146a1be0e8c80878090f39c0eaa15d2eb13
 2007-11-15 14:21:01 -05:00
Korey Sewell 641ee83e40 add core specific parameter to BaseCPU params 
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extra : convert_revision : 15c5995e3acf23a45c712891fd06ef273584f7e8
 2007-11-15 14:18:56 -05:00
Korey Sewell 7ba65aecaa Add CoreSpecific type to all archs 
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extra : convert_revision : 659786bf6489ab6151e47fbf1f4c0a723262fce2
 2007-11-15 14:17:21 -05:00
Korey Sewell 789153dff6 Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp" 
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extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
 2007-11-15 03:10:41 -05:00
Korey Sewell 375ddf8d25 branch merge 
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extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
 2007-11-15 00:14:20 -05:00
Ali Saidi 7c8e4ca3a3 Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once. 
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extra : convert_revision : 3bac9bd7fd93fcadf764e2991c5b029f2c745c08
 2007-11-14 23:42:08 -05:00
Korey Sewell 2820a448e2 comment and spacing 
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extra : convert_revision : b3acde37bc11919700c257eae58ea9e0f66c9786
 2007-11-14 15:33:43 -05:00
Korey Sewell 5f7879a935 Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world 
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extra : convert_revision : 0944e7661934baddca1f1a895af0b75be2d96b10
 2007-11-14 06:24:47 -05:00
Korey Sewell bfdd2f379b remove unnecessary debug messages I added 
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extra : convert_revision : 5c23218fd1b899fa7fe42701f7cb2f6033f7a583
 2007-11-14 06:18:58 -05:00
Korey Sewell 2692590049 Add in files from merge-bare-iron, get them compiling in FS and SE mode 
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extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
 2007-11-13 16:58:16 -05:00
Gabe Black 5772e3cada X86: Make microcode use presegmentation RIPs and the rest of m5 use post segmentation RIPS. 
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extra : convert_revision : d8cda7c8b9a2afb8a9d601b6d61529a96c5f87fe
 2007-11-13 01:31:43 -08:00