Commit graph

8909 commits

Author SHA1 Message Date
Geoffrey Blake a64319f764 ARM: IT doesn't need to be serializing. 2012-03-21 10:34:06 -05:00
Andrew Lukefahr b4e5be717d O3: Fix sizing of decode to rename skid buffer. 2012-03-21 10:34:06 -05:00
Koan-Sin Tan 0376422c0b ARM: Add RTC to PBX System 2012-03-21 10:34:05 -05:00
Brian Grayson 565c1de4a8 O3: Fix size of skid buffer between fetch and decode when widths are different 2012-03-21 10:34:05 -05:00
Ali Saidi 1981ba21ca ARM: Fix uninitialized value in ARM RTC model. 2012-03-21 10:34:05 -05:00
Tushar Krishna c9e4bca8d8 Garnet: Stats at vnet granularity + code cleanup
This patch
(1) Moves redundant code from fixed and flexible networks to BaseGarnetNetwork.
(2) Prints network stats at vnet granularity.
2012-03-19 17:34:17 -04:00
Andreas Hansson 72538294fb gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).
2012-03-19 06:36:09 -04:00
Andreas Hansson adb8621031 clang: Fix recently introduced clang compilation errors
This patch makes the code compile with clang 2.9 and 3.0 again by
making two very minor changes. Firt, it maintains a strict typing in
the forward declaration of the BaseCPUParams. Second, it adds a
FullSystemInt flag of the type unsigned int next to the boolean
FullSystem flag. The FullSystemInt variable can be used in
decode-statements (expands to switch statements) in the instruction
decoder.
2012-03-19 06:35:04 -04:00
Andreas Hansson a444a6f8d6 scripts: Fix to ensure that port connection count is always set
This patch ensures that the port connection count is set to zero in those
cases when the port is not connected.
2012-03-19 06:34:02 -04:00
Nilay Vaish f02eec93d6 ruby_fs.py: Add call to createInterruptController() 2012-03-16 07:47:03 -05:00
Nilay Vaish 13a5e9b7b5 FSConfig.py: fix a typo makeLinuxAlphaRubySystem 2012-03-16 07:46:45 -05:00
Marc Orr 24fe7cdf00 build: remove implicit-cache setting of scons from recent build faster patch 2012-03-16 03:29:07 -07:00
Nilay Vaish bb7be54d73 se.py: Changes to ruby portion due to SE/FS merge
With the SE/FS merge, interrupt controller is created irrespective of the
mode. This patch creates the interrupt controller when Ruby is used and
connects its ports.
2012-03-11 16:51:38 -05:00
Brian Grayson 98185658c5 O3: Add fatal when fetchWidth > Impl::MaxWidth. 2012-03-11 10:20:54 -04:00
Ali Saidi d2a0db7fe9 ARM: Fix memory starting at non-zero address and exceeding max mem for a system. 2012-03-09 16:45:47 -05:00
Ali Saidi 470051345a ARM: Update stats for CBNZ fix. 2012-03-09 15:33:07 -05:00
Brian Grayson 9a9a4a0780 ARM: Fix branch prediction issue with CB(N)Z instruction 2012-03-09 15:32:41 -05:00
Ali Saidi 927bba9d60 ARM: Update stats for valgrind fix and replace config.inis which are out of date. 2012-03-09 09:59:29 -05:00
Geoffrey Blake 69d229ce28 O3/Ozone: Eliminate dead code counting software prefetch insts
Eliminates dead code in the O3 and Ozone CPU models that counted
software prefetch instructions separately for the ALPHA ISA only.
2012-03-09 09:59:28 -05:00
Geoffrey Blake da0d67c3d6 CheckerCPU: Make some basic regression tests for CheckerCPU
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
2012-03-09 09:59:28 -05:00
Geoffrey Blake 98cf57fb89 CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM.  This patch adds the appropriate function
stubs to allow compilation.
2012-03-09 09:59:28 -05:00
Geoffrey Blake 043709fdfa CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files.  Also merges with the SE/FS changes.
2012-03-09 09:59:27 -05:00
Ali Saidi df05ffab12 ARM: Don't reset CPUs that are going to be switched in. 2012-03-09 09:59:26 -05:00
Ali Saidi 3ce2d0fad0 System: Move code in initState() back into constructor whenever possible.
The change to port proxies recently moved code out of the constructor into
initState(). This is needed for code that loads data into memory, however
for code that setups symbol tables, kernel based events, etc this is the wrong
thing to do as that code is only called when a checkpoint isn't being restored
from.
2012-03-09 09:59:26 -05:00
Ali Saidi ec1ef24895 ARM: Fix valgrind reported error on O3 that was causing minor stats changes. 2012-03-09 09:59:26 -05:00
Ali Saidi eaa994e7f6 cache: Allow main memory to be at disjoint address ranges. 2012-03-09 09:59:25 -05:00
Gabe Black cda4c2d280 Fix the SPARC fs regression by adding a call to createInterruptController. 2012-03-08 02:10:03 -08:00
Marc Orr eb43883bef build scripts: Made minor modifications to reduce build overhead time.
1. --implicit-cache behavior is default.
2. makeEnv in src/SConscript is conditionally called.
3. decider set to MD5-timestamp
4. NO_HTML build option changed to SLICC_HTML (defaults to False)
2012-03-06 19:07:41 -08:00
Andreas Hansson 75681d3c1b Stats: Update stats for changeset 8868
Changeset 8868 slightly changes the statistics for the parser and
bzip2 regressions for ARM o3-timing. This patch merely updates the
statistics to reflect these changes.
2012-03-06 11:14:54 -05:00
Steve Reinhardt 3418ebb5f8 SConstruct: rename and document AddM5Option
Got rid of gratuitous M5 reference in the function name.
In the process, wondered why we have this function at all and
spent time trying to get rid of it and eventually firgured out
why it's needed.  Put the answer in a comment so we don't have
to wonder again.
2012-03-02 14:05:00 -08:00
Steve Reinhardt f71a5c5e62 SConstruct: update comments & doc strings
Lots of references to 'M5' still, and some to SE/FS
2012-03-02 13:53:52 -08:00
Steve Reinhardt fd2d5ae2af DynInst: get rid of dead MyHash code.
Not sure what this was ever used for, but it
doesn't seem used anymore.
2012-03-02 09:17:42 -08:00
Andreas Hansson 32eae8094d CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.

The patch also adds the "createInterruptController" call to a number
of the regression scripts.
2012-03-02 09:21:48 -05:00
Andreas Hansson c0b9f324bf Stats: Fix the realview regression stats after nvmem move
This patch updates the realview regressions stats to reflect that nvmem
moved in the object hierarchy and is now under system.realview.
2012-03-02 09:18:50 -05:00
Andreas Hansson adc419a13a Ruby: Rename RubyPort::sendTiming to avoid overriding base class
This patch renames the sendTiming member function in the RubyPort to
avoid inadvertently hiding Port::sendTiming (discovered through some
rather painful debugging). The RubyPort does, in fact, rely on the
functionality of the queued port and the implementation merely
schedules a send the next cycle. The new name for the member function
is sendNextCycle to better reflect this behaviour.

In the unlikely event that we ever shift to using C++11 the member
functions in Port should have a "final" identifier to prevent any
overriding in derived classes.
2012-03-02 09:16:50 -05:00
Ali Saidi b129d7ce00 ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.
New kernel code verifies that multi-processor extensions are available
before booting secondary CPUs.
2012-03-02 08:18:19 -06:00
Ali Saidi 96e37eb17c ARM: FIx missing cf controller connection. 2012-03-01 22:43:23 -06:00
Chander Sudanthi 357fb0a185 VNC: spacing
Fixed some spacing in a switch statement
2012-03-01 17:26:36 -06:00
Ali Saidi 91b737ed48 ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
2012-03-01 17:26:31 -06:00
Ali Saidi 3876105bdb ARM: Add RTC device for ARM platforms.
This change implements a PL031 real time clock.

--HG--
rename : src/dev/arm/timer_sp804.cc => src/dev/arm/rtc_pl031.cc
rename : src/dev/arm/timer_sp804.hh => src/dev/arm/rtc_pl031.hh
2012-03-01 17:26:31 -06:00
Matt Horsnell 08187e3916 ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.
2012-03-01 17:26:31 -06:00
Ali Saidi d907d0ec72 Cache: Fix an issue with LRU when bonus block is used to complete transaction.
The block is never inserted because it's the one extra block in the cache, but
it can be invalidated twice in a row. In that case the block doesn't have a
new master id (beacuse it was never inserted), however it is valid and
the accounting goes wrong at that point.
2012-03-01 17:26:31 -06:00
Dam Sunwoo 86d1042d9f ARM: move kernel func event to correct location.
With the recent series of patches, the symbol table loading moved from
"construct" time to "init" time, but the kernel function event
callback registration was left behind. This patch moves it to the
proper location.
2012-03-01 17:26:31 -06:00
Giacomo Gabrielli d51478db4e ARM: fix bits-to-fp conversion function declarations.
Add extra declarations to allow the compiler to pick up the right function.
Please note that these declarations have been added as part of the
clang-related changes.
2012-03-01 17:26:30 -06:00
Nilay Vaish 4b32c9fb4d x86: Fix x86 TLB and Walker
This patch adds a function to X86 tlb that returns the
walker port. This port is required for correctly connecting
the walker ports for the cpu just switched in
2012-03-01 11:37:03 -06:00
Nilay Vaish c80af04d7d x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for
cpus that will be switched in later
2012-03-01 11:37:02 -06:00
Nilay Vaish e11847bfa9 Config: make option ruby available always 2012-03-01 11:36:59 -06:00
Andreas Hansson e5ac647fc9 MEM: Make all the port proxy members const
This is a trivial patch that merely makes all the member functions of
the port proxies const. There is no good reason why they should not
be, and this change only serves to make it explicit that they are not
modified through their use.
2012-02-29 04:47:51 -05:00
Andreas Hansson 88abdc0fad SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
This patch fixes a compilation error that occurs with gcc >= 4.6.1,
caused by swig not including cstddef and not using the std:: namespace
prefix for ptrdiff_t. There is an old patch,
http://reviews.m5sim.org/r/913/ that no longer applies cleanly and
this might be re-iterating the same issue.

We work around the problem by always enforcing the inclusion of
cstddef in all swig interface declarations, and also by explicitly
using std::ptrdiff_t.
2012-02-29 04:26:58 -05:00
Steve Reinhardt 13e14ba93c EIO: update stats (mostly order change, some renames) 2012-02-29 01:51:39 -05:00