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Author SHA1 Message Date
Nathan Binkert b2036bfda8 Command line option to print out List of SimObjects and their parameters 2008-06-14 21:51:08 -07:00
Nathan Binkert bbeb8082a5 main: add .m5/options.py processing. This file is processed before 
arguments are parsed so that they can change the default options for
various config parameters.
 2008-06-14 21:16:00 -07:00
Nathan Binkert fc48d1dcf5 Add .m5 configuration directory 2008-06-14 21:15:59 -07:00
Nathan Binkert 779c31077c python: Separate the options parsing stuff. Remove options parsing stuff from 
main.py so things are a bit more obvious.
 2008-06-14 21:15:58 -07:00
Nathan Binkert 4afdc40d70 params: Fix the memory bandwidth parameter 2008-06-14 20:42:45 -07:00
Nathan Binkert 3d2e7797cc params: Fix floating point parameters 2008-06-14 20:39:31 -07:00
Nathan Binkert f82d4e2364 python: Move various utility classes into a new m5.util package so 
they're all in the same place.  This also involves having just one
jobfile.py and moving it into the utils directory to avoid
duplication.  Lots of improvements to the utility as well.

--HG--
rename : src/python/m5/attrdict.py => src/python/m5/util/attrdict.py
rename : util/pbs/jobfile.py => src/python/m5/util/jobfile.py
rename : src/python/m5/util.py => src/python/m5/util/misc.py
rename : src/python/m5/multidict.py => src/python/m5/util/multidict.py
rename : util/stats/orderdict.py => src/python/m5/util/orderdict.py
 2008-06-14 20:19:49 -07:00
Nathan Binkert fe325c7f43 MemReq: Add option to reset the time on a request. 2008-06-14 19:39:01 -07:00
Nathan Binkert ce43e46576 Fix various SWIG warnings 2008-06-14 12:57:21 -07:00
Nathan Binkert 7a58b5a38a Add missing dependencies on .i files 2008-06-14 12:10:50 -07:00
Nathan Binkert 2d037682ff scons: proper fix for hg version stuff 2008-06-14 10:30:18 -07:00
Nathan Binkert fe4fd9f414 scons: fix program_info.cc generation 2008-06-13 17:34:22 -07:00
Steve Reinhardt dace77dc4a Automated merge with ssh://m5sim.org//repo/m5 2008-06-13 01:59:10 -04:00
Steve Reinhardt caccbd1edc Get rid of bogus bus assertion. 
It runs out that if a MemObject turns around and does a send in its
receive callback, and there are other sends already scheduled, then
it could observe a state where it's not at the head of the list but
the bus's sendEvent is not scheduled (because we're still in the
middle of processing the prior sendEvent).
 2008-06-13 01:33:49 -04:00
Steve Reinhardt 024ec4c5c3 Get rid of bogus cache assertion. 
I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.
 2008-06-13 01:29:20 -04:00
Ali Saidi 907b28cc62 HG: Add compiled hg revision and date to the standard M5 output. 2008-06-13 01:09:04 -04:00
Gabe Black 2b4874449c Alpha: Get rid of an old include of a non-existant file. 2008-06-12 01:54:21 -04:00
Gabe Black 7be8e671f1 Params: Allow nested namespaces in cxx_namespace 2008-06-12 01:00:29 -04:00
Gabe Black 5b5875341c X86: Make the cpuid processor identifier return a real string. 2008-06-12 01:00:19 -04:00
Gabe Black c625cf0ae1 X86: Make the code compile as 32 bit. 2008-06-12 01:00:05 -04:00
Gabe Black 23c04b8c66 Params: Remove an unnecessary include. 2008-06-12 00:59:58 -04:00
Gabe Black bceaa257a3 X86: Make the e820 table manually or automatically configurable from python. 2008-06-12 00:58:36 -04:00
Gabe Black 4f4ff17578 X86: Make the disassembly for halt conform with the other microops. 2008-06-12 00:58:27 -04:00
Gabe Black 31d40ad7c2 X86: Implement and hook up STI and CLI instructions. 2008-06-12 00:58:19 -04:00
Gabe Black da20c0ec54 X86: Make sure there's something to catch when the kernel messes with ports "behind" the pci config magic ports. 2008-06-12 00:58:13 -04:00
Gabe Black 1f5b992b58 X86: Make the platform object initialize channel 0 of the PIT. 2008-06-12 00:56:54 -04:00
Gabe Black 16e26fbf03 X86: Hook the speaker device to the pit device. 2008-06-12 00:56:17 -04:00
Gabe Black da7f512067 Timer: Fill out the periodic modes a little. 2008-06-12 00:56:07 -04:00
Gabe Black 4f9a0402f6 Dev: Seperate the 8254 timer from tsunami and use it in that and the PC. 2008-06-12 00:54:48 -04:00
Gabe Black 0368ccdeda BitUnion: Take out namespace declaration so bitunions can be declared inside classes. 2008-06-12 00:54:32 -04:00
Gabe Black 81936ae2ed X86: Add an event for the apic timer timeout. It doesn't get used yet. 2008-06-12 00:54:19 -04:00
Gabe Black 6b8d0363ee X86: Rename the divide count register to divide configuration. 2008-06-12 00:54:12 -04:00
Gabe Black b10742ee2b X86: Make the apic isr and irr work. 2008-06-12 00:54:05 -04:00
Gabe Black 69000baef3 X86: Make the apic task priority register work. 2008-06-12 00:54:01 -04:00
Gabe Black e9c481ea4a X86: Make the logical destination and destination format work. 2008-06-12 00:53:50 -04:00
Gabe Black ed23a4970b X86: Make the apic ID register work. 2008-06-12 00:53:43 -04:00
Gabe Black 8a6723e038 X86: Make the apic version register work. 2008-06-12 00:53:37 -04:00
Gabe Black 8d2416c6e9 X86: Implement a partial, sort of correct version of the protected mode variant of iret. 2008-06-12 00:53:01 -04:00
Gabe Black 66f54a6037 X86: Change how segment loading is performed. 2008-06-12 00:52:12 -04:00
Gabe Black 129831c116 X86: Make pushes and pops use the stack size instead of the data size. 2008-06-12 00:51:57 -04:00
Gabe Black b05299253f X86: In non 64bit mode, throw a fault when a NULL segment is accessed. 2008-06-12 00:51:50 -04:00
Gabe Black a8384311d5 X86: Take advantage of the new meta register. 2008-06-12 00:51:14 -04:00
Gabe Black d4e7c7edd3 X86: Keep handy values like the operating mode in one register. 2008-06-12 00:50:25 -04:00
Gabe Black fa7c81c6df X86: Change what the microop chks does. 
Instead of computing the segment descriptor address, this now checks if a
selector value/descriptor are legal for a particular purpose.
 2008-06-12 00:50:10 -04:00
Gabe Black 6bd9cf3594 X86: Add a microop to read a segments attribute register. 2008-06-12 00:50:05 -04:00
Gabe Black e0c20386ac X86: Add microops and supporting code to manipulate the whole rflags register. 2008-06-12 00:49:50 -04:00
Gabe Black 2bb8933f78 X86: Add microops which panic, fatal, warn, and warn_once. 2008-06-12 00:49:25 -04:00
Gabe Black bbc1f394ff X86: Truncate descriptors to 16 bits. 2008-06-12 00:49:16 -04:00
Gabe Black 6106b05b6e X86: Redo BSF. 2008-06-12 00:48:58 -04:00
Gabe Black dfc2d44ea3 X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate. 2008-06-12 00:48:46 -04:00
Gabe Black de6eeaaa27 X86: Make string instructions work when rcx=0. 2008-06-12 00:48:15 -04:00
Gabe Black 8688ef3fe5 X86: Have all 8 machine check registers since the kernel assumes they're there. 2008-06-12 00:48:02 -04:00
Gabe Black a8e3001df8 X86: Bypass unaligned access support for register addressed MSRs. 2008-06-12 00:47:25 -04:00
Gabe Black b3e55339f9 X86: Remove enforcement of APIC register access alignment. Panic if more than one register is accessed at a time. 2008-06-12 00:46:22 -04:00
Gabe Black 8e2991b529 X86: Fix the implementation of BSF. 2008-06-12 00:46:04 -04:00
Gabe Black 16e189fad2 X86: Bit scan forward/reverse were accidentally transposed. 2008-06-12 00:45:52 -04:00
Gabe Black 254cc07650 X86: Fix a byte register indexing issue in the sign extending move from memory microcode. 2008-06-12 00:45:22 -04:00
Gabe Black 8501a90f59 X86: Add in some support for the tsc register. 2008-06-12 00:39:10 -04:00
Gabe Black d093fcb079 CPU: Make the simple cpu trace data for loads/stores. 2008-06-12 00:35:50 -04:00
Ali Saidi 5797ff1016 X86: Fix building on *BSD hosts 2008-06-11 10:54:12 -04:00
Ali Saidi fd3e661cd3 SCons: Fix more SCons version issues 2008-06-11 10:54:08 -04:00
Ali Saidi f5e36d156d IGbE: Implement sending packet that is contained in more than 2 descriptors. 
--HG--
extra : convert_revision : 8fb7d5fad5cb840f69c31aa8b331dbe09e46ee9d
 2008-05-20 16:06:56 -04:00
Stephen Hines b7af65f414 SCons: Fixing SCons bug 2006 issues for non-alpha ISAs 
--HG--
extra : convert_revision : 26e3edef06d6f82aaf162825c151d18faadd6e72
 2008-05-20 14:04:53 -04:00
Ali Saidi e71a5270a2 Make sure that output files are always checked success before they're used. 
Make OutputDirectory::resolve() private and change the functions using
resolve() to instead use create().

--HG--
extra : convert_revision : 36d4be629764d0c4c708cec8aa712cd15f966453
 2008-05-15 19:10:26 -04:00
Ali Saidi 4a4317ae18 SCons: More scons fixing for SCons bug 2006 
--HG--
extra : convert_revision : d3656ab1e3c18251d4bcf6f5a31103d4b2dfdc43
 2008-05-06 16:22:14 -04:00
Ali Saidi 8af6dc118c SCons: add comments to SConscript documenting bug workaround 
--HG--
extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
 2008-04-10 15:38:10 -04:00
Ali Saidi fe12f38353 PhysicalMemory: Add parameter for variance in memory delay. 
--HG--
extra : convert_revision : b931472e81dedb650b7accb9061cb426f1c32e66
 2008-04-10 14:44:52 -04:00
Ali Saidi ed27c4c521 SCons: Manually specifying header only directories with Dir() works around the problem 
--HG--
extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
 2008-04-08 11:08:26 -04:00
Ali Saidi 1605fbebc8 IGbE: Fix bug that limits wire performance a bit 
--HG--
extra : convert_revision : 3f93c17f647a6955dab861da211174de856ee02c
 2008-03-25 15:58:54 -04:00
Steve Reinhardt ba1f7d31e0 Automated merge with ssh://daystrom.m5sim.org//repo/m5 
--HG--
extra : convert_revision : 7922848bb1145bcb2ee07d672d21cfe2dd98fc03
 2008-03-25 10:04:52 -04:00
Steve Reinhardt 29be31ce31 Fix handling of writeback-induced writebacks in atomic mode. 
--HG--
extra : convert_revision : 4fa64f8a929f1aa36a9d5a71b8d1816b497aca4c
 2008-03-25 10:01:21 -04:00
Gabe Black 93dd1978a7 X86: Put an RTC into the CMOS part of the southbridge. 
--HG--
extra : convert_revision : a614373236fe75db6e6181fc152a02b541a131f3
 2008-03-25 02:15:23 -04:00
Gabe Black e5bdae15f3 Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it. 
--HG--
extra : convert_revision : 1e7f5185654ed0845678c2169c702d3b977159ed
 2008-03-25 02:15:06 -04:00
Gabe Black af9a57566a X86: Turn #defines into consts. 
--HG--
extra : convert_revision : c0416de5d88ca39f54494418768e68a93aa4f2aa
 2008-03-25 02:09:18 -04:00
Gabe Black 48409ca512 X86: Start implementing the south bridge stuff. 
--HG--
extra : convert_revision : 92918c05eb3363155d78889bdab17baa8eae9dca
 2008-03-25 02:08:54 -04:00
Gabe Black b0c52885ce X86: Change the Opteron platform to be the PC platform. 
--HG--
extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
 2008-03-25 02:06:53 -04:00
Steve Reinhardt 623dd7ed3a Delete the Request for a no-response Packet 
when the Packet is deleted, since the requester
can't possibly do it.

--HG--
extra : convert_revision : 8571b144ecb3c70efc06d09faa8b3161fb58352d
 2008-03-24 01:08:02 -04:00
Steve Reinhardt 93ab43288a Don't FastAlloc MSHRs since we don't allocate them on the fly. 
--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
 2008-03-24 01:08:02 -04:00
Steve Reinhardt 627592c2f2 Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options. 
--HG--
extra : convert_revision : 56a7f646f2ac87019c78ba7fa62c5f4bdc00ba44
 2008-03-24 01:08:02 -04:00
Steve Reinhardt 407710d387 Fix cache problem with writes to tempBlock 
getting wrong writeback address.

--HG--
extra : convert_revision : 023dfb69c227c13a69bfe2744c6af75a45828b0b
 2008-03-22 22:17:15 -04:00
Gabe Black 3fe1af7952 MIPS: Check endianness of binaries in SE mode. 
--HG--
extra : convert_revision : e6c4bda6078eb68a26f8834411f744078c6bf5a9
 2008-03-20 02:10:21 -04:00
Steve Reinhardt b051ae6acc Fix a few Packet memory leaks. 
--HG--
extra : convert_revision : 00db19f0698c0786f0dff561eea9217860a5a05a
 2008-03-17 03:08:28 -04:00
Steve Reinhardt 131c65f429 Restructure bus timing calcs to cope with pkt being deleted by target. 
--HG--
extra : convert_revision : db8497e73a44f2a06aab121e797e88b4c0c31330
 2008-03-17 03:07:38 -04:00
Steve Reinhardt 19c367fa8f Fix subtle cache bug where read could return stale data 
if a prior write miss arrived while an even earlier
read miss was still outstanding.

--HG--
extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a
 2008-03-15 05:03:55 -07:00
Gabe Black 50946b1673 Merge 
--HG--
extra : convert_revision : ec5f41b2007ade15f6f4c4a1533e50f9cba2798e
 2008-03-06 21:09:15 -05:00
Gabe Black a245b0eedf X86: Refine the local APIC. 
--HG--
extra : convert_revision : 2789c54ed555fed2f2a333fcc7dc6454f294ebf2
 2008-03-06 20:37:28 -05:00
Vilas Sridharan 21fd15ad9a O3CPU: Don't call dumpInsts if DEBUG is not defined 
--HG--
extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
 2008-03-06 00:27:09 -05:00
Gabe Black 66aaabf4ae X86: Don't map the local APIC into the physical address space in SE mode. 
--HG--
extra : convert_revision : b7103974b12130bbf43583c4cb5294b808add208
 2008-03-01 00:05:12 -05:00
Steve Reinhardt 19dfde2317 Automated merge with ssh://daystrom.m5sim.org//repo/m5 
--HG--
extra : convert_revision : f4bcd342e7abb86ca83840b723e6ab0b861ecf5b
 2008-02-27 18:18:56 -05:00
Korey Sewell 8fb74c238c Add comments in code to describe bug conditions. 
This should help if somebody gets to the bug
fix before me (or someone else)...

--HG--
extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
 2008-02-27 17:50:29 -05:00
Korey Sewell b45cf21a8e Fix Load/Store Queue squashing after a SMT thread is removed but ensuring 
you are squashing from the current instruction # causing the thread exit.

--HG--
extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
 2008-02-27 16:53:08 -05:00
Korey Sewell 34715cc691 Fix offset in removeThread() function so that float registers start freeing up 
from the right point (#32 usually) instead of restarting at 0 and double-freeing.

Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.

--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
 2008-02-27 16:48:33 -05:00
Steve Reinhardt e6d6adc731 Revamp cache timing access mshr check to make stats sane again. 
--HG--
extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
 2008-02-26 22:03:28 -08:00
Rick Strong fcfc8b8c4f Configs: Make using Simpoints easier with some config files that support them easily 
--HG--
extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd
 2008-02-27 00:35:09 -05:00
Gabe Black 43ecce5fda X86: Put in initial implementation of the local APIC. 
--HG--
extra : convert_revision : 1708a93d96b819e64ed456c75dbb5325ac8114a8
 2008-02-26 23:39:53 -05:00
Gabe Black 98d2ca403e X86: Implement the INVLPG instruction and the TIA microop. 
--HG--
extra : convert_revision : 31db1ee082f6c3ca5443cba1eb335e408661ead2
 2008-02-26 23:39:22 -05:00
Gabe Black 8b4796a367 TLB: Make a TLB base class and put a virtual demapPage function in it. 
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
 2008-02-26 23:38:51 -05:00
Gabe Black 7bde0285e5 X86: Get PCI config space to work, and adjust address space prefix numbering scheme. 
--HG--
extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
 2008-02-26 23:38:01 -05:00
Steve Reinhardt bdf3323915 Cache: better comments particularly regarding writeback situation. 
--HG--
extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
 2008-02-26 20:17:26 -08:00
Gabe Black ec1a4cbbc7 Bus: Fix the bus timing to be more realistic. 
--HG--
extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc
 2008-02-26 02:20:08 -05:00