Commit graph

4397 commits

Author SHA1 Message Date
Ali Saidi
776c075917 O3: reset architetural state by calling clear() 2010-11-15 14:04:05 -06:00
Ali Saidi
5f59e195d6 ARM: Add comment about the organization of the IT state register 2010-11-15 14:04:05 -06:00
Giacomo Gabrielli
0058927190 CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
Min Kyu Jeong
745df74fe0 O3: prevent a squash when completeAcc() modifies misc reg through TC.
This happens on ARM instructions when they update the IT state bits.
Code and associated comment was copied from execute() and initiateAcc() methods
2010-11-15 14:04:04 -06:00
Ali Saidi
4a1814bd52 ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.
Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.
2010-11-15 14:04:04 -06:00
Ali Saidi
d4767f440a SCons: Cleanup SCons output during compile 2010-11-15 14:04:04 -06:00
William Wang
6fbea15064 ARM: Add a Keyboard Mouse Interface controller 2010-11-15 14:04:03 -06:00
William Wang
fc1eeafc94 ARM: Implement a CLCD Frame buffer 2010-11-15 14:04:03 -06:00
William Wang
80db6a5ecb ARM: Add support for GDB on ARM
--HG--
rename : src/arch/alpha/remote_gdb.cc => src/arch/arm/remote_gdb.cc
2010-11-15 14:04:03 -06:00
Ali Saidi
06864386a1 ARM: Make utility.hh meet style guidelines 2010-11-15 14:04:03 -06:00
Ali Saidi
d7b8efa0df ARM: Add support for a dumb IDE controller 2010-11-15 14:04:03 -06:00
Ali Saidi
13931b9b82 ARM: Cache the misc regs at the TLB to limit readMiscReg() calls. 2010-11-15 14:04:03 -06:00
Ali Saidi
4c2e5c282b ARM: Add support for switching CPUs 2010-11-15 14:04:03 -06:00
Ali Saidi
08c5673d56 ARM: Use the correct delete operator for RFE 2010-11-15 14:04:03 -06:00
Ali Saidi
50431f4eab ARM: Fix SRS instruction to micro-code memory operation and register update.
Previously the SRS instruction attempted to writeback in initiateAcc() which
worked until a recent change, but was incorrect.
2010-11-15 14:04:03 -06:00
Ali Saidi
16f210da37 CPU: Fix bug when a split transaction is issued to a faster cache
In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
2010-11-15 14:04:03 -06:00
Ali Saidi
265e145db2 ARM: Do something predictable for an UNPREDICTABLE branch. 2010-11-15 14:04:03 -06:00
Gabe Black
46472279c0 Params: Fix an off by one error and a misleading comment. 2010-11-11 11:58:09 -08:00
Gabe Black
3c237f44c9 SimObject: Add a comment near clear_child that it's unlikely to be called. 2010-11-11 11:41:13 -08:00
Gabe Black
cdc585e0e8 SPARC: Clean up some historical style issues. 2010-11-11 02:03:58 -08:00
Gabe Black
2fd9dc19cd SimObject: Use "self" when calling the clear_child method. 2010-11-09 10:45:02 -08:00
Gabe Black
388124492e X86: Fix X86_FS compilation. 2010-11-08 12:43:38 -08:00
Ali Saidi
057b451773 ARM: Add some TLB statistics for ARM 2010-11-08 13:58:25 -06:00
Ali Saidi
a1e8225975 ARM: Add checkpointing support 2010-11-08 13:58:25 -06:00
Ali Saidi
432fa0aad6 ARM: Add support for M5 ops in the ARM ISA 2010-11-08 13:58:24 -06:00
Ali Saidi
0f2bbe15dd ARM: Keep the warnings to a minimum.
These warnings still need to be addresses, but pages of them is
counterproductive.
2010-11-08 13:58:24 -06:00
Ali Saidi
c779af4e12 Mem: Finish half-baked support for mmaping file in physmem.
Physmem has a parameter to be able to mem map a file, however
it isn't actually used. This changeset utilizes the parameter
so a file can be mmapped.
2010-11-08 13:58:24 -06:00
Ali Saidi
ea1167dd9f Bus: Have the I/O devices that return address ranges print them out.
This way we actually get device names associated with the devices.
2010-11-08 13:58:24 -06:00
Ali Saidi
e6c31ceb2b ARM: Don't return the result of a table walk the same cycle it's completed.
The L1 cache may have been accessed to provide this data, which confuses
it, if it ends up being accesses twice in one cycle. Instead wait 1 tick
which will force the timing simple CPU to forward to its next clock cycle
when the translation completes.

Also prevent multiple outstanding table walks from occuring at once.
2010-11-08 13:58:24 -06:00
Ali Saidi
cdacbe734a ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.

On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.

On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.
2010-11-08 13:58:22 -06:00
Ali Saidi
f4f5d03ed2 ARM: Make all ARM uops delayed commit. 2010-11-08 13:58:22 -06:00
Ali Saidi
0ea794bcf4 sim: Use forward declarations for ports.
Virtual ports need TLB data which means anything touching a file in the arch
directory rebuilds any file that includes system.hh which in everything.
2010-11-08 13:58:22 -06:00
Gabe Black
72b5262278 scons: Replace the build_dir parameter to SConscript with variant_dir.
The build_dir parameter name has been deprecated and replaced with
variant_dir. This change switches us over to avoid warning spew in newer
versions of scons.
2010-11-06 17:48:58 -07:00
Gabe Black
6f4bd2c1da ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
2010-10-31 00:07:20 -07:00
Gabe Black
373154a25a X86: Fault on divide by zero instead of panicing. 2010-10-29 02:20:47 -07:00
Gabe Black
7378424b14 X86: Make syscalls also serialize after. 2010-10-29 02:20:46 -07:00
Gabe Black
d5dbd91f3d O3: Get rid of a bunch of commented out lines. 2010-10-24 00:43:32 -07:00
Gabe Black
2eae11be64 X86: Make nop a regular, non-microcoded instruction.
Code in the CPUs that need a nop to carry a fault can't easily deal with a
microcoded nop. This instruction format provides for one that isn't.

--HG--
rename : src/arch/x86/isa/formats/syscall.isa => src/arch/x86/isa/formats/nop.isa
2010-10-22 00:24:15 -07:00
Gabe Black
23f6196d61 X86: Implement genMachineCheckFault.
Even though this shouldn't ever be used, it might get called speculatively and
shouldn't panic.
2010-10-22 00:24:08 -07:00
Gabe Black
255685534a X86: Make syscall instructions non-speculative in SE. 2010-10-22 00:23:50 -07:00
Gabe Black
29676286c8 ISA: Simplify various implementations of completeAcc. 2010-10-22 00:23:19 -07:00
Gabe Black
bc49381287 ARM: Don't pretend to writeback registers in initiateAcc. 2010-10-22 00:22:59 -07:00
Steve Reinhardt
45aebaccde cache: minor SC assertion fix
Thanks to Joe Gross for finding/testing this.
2010-10-18 13:05:15 -07:00
Gabe Black
968447db66 MIPS: Get rid of the backdoor device copy/pasted from and only used in Alpha. 2010-10-17 23:15:53 -07:00
Gabe Black
b289966a78 Mem: Reclaim some request flags used by MIPS for alignment checking.
These flags were being used to identify what alignment a request needed, but
the same information is available using the request size. This change also
eliminates the isMisaligned function. If more complicated alignment checks are
needed, they can be signaled using the ASI_BITS space in the flags vector like
is currently done with ARM.
2010-10-16 00:00:54 -07:00
Gabe Black
ab9f062166 GetArgument: Rework getArgument so that X86_FS compiles again.
When no size is specified for an argument, push the decision about what size
to use into the ISA by passing a size of -1.
2010-10-15 23:57:06 -07:00
Gabe Black
b197a542b4 SPARC: Get rid of the copy/pasted StackTrace stolen from Alpha. 2010-10-14 14:02:23 -07:00
Gabe Black
930c653270 Mem: Change the CLREX flag to CLEAR_LL.
CLREX is the name of an ARM instruction, not a name for this generic flag.
2010-10-13 01:57:31 -07:00
Gabe Black
b273e0be33 X86: Detect attempts to load a 32 bit kernel and panic. 2010-10-10 20:39:26 -07:00
Gabe Black
157d6f9c2f SPARC: Make SPARC's ISA's clear function initialize everything it should.
Also make it not set some pointers to NULL potentially introducing a memory
leak. That should be done in the constructor.
2010-10-10 20:38:05 -07:00
Gabe Black
63fa65613e Alpha: Force all the IPRs to an initial, determinstic value when cleared. 2010-10-10 20:37:50 -07:00
Gabe Black
b4a76f0b0b Alpha: Initialize the data TLB mode IPR. 2010-10-10 20:37:39 -07:00
Gabe Black
9268f895d5 UART: Make the 8250's MCR return a deterministic value.
This change makes the 8250 device return the value it has for the MCR when
read instead of leaving the packet data unmodified/uninitialized. The value
the UART has for the MCR may not be right, but that's a seperate issue that
apparently hasn't caused any problems to date.
2010-10-09 12:41:31 -07:00
Gabe Black
d4492190e6 Alpha: Fix Alpha NumMiscArchRegs constant.
Also add asserts in O3's Scoreboard class to catch bad indexes.
2010-10-04 11:58:06 -07:00
Ali Saidi
538acf2082 Power: Fix compile error from previous push. 2010-10-01 17:57:56 -05:00
Ali Saidi
dcaa0668ae ARM: Make the TLB a little bit faster by moving most recently used items to front of list 2010-10-01 16:04:04 -05:00
Ali Saidi
f0c0b8a7f6 ARM: Add a fake flash controller so that unmodified linux can boot
With this change an unmodified Linux kernel can boot in M5.
2010-10-01 16:04:02 -05:00
Prakash Ramrakhyani
9792bbc324 ARM: Fix some subtle bugs in the GIC
The GIC code can write to the registers with 8, 16, or 32 byte
accesses which could set/clear different numbers of interrupts.
2010-10-01 16:04:00 -05:00
Ali Saidi
521d68c82a ARM: Implement functional virtual to physical address translation
for debugging and program introspection.
2010-10-01 16:03:27 -05:00
Ali Saidi
518b5e5b1c Debug: Implement getArgument() and function skipping for ARM.
In the process make add skipFuction() to handle isa specific function skipping
instead of ifdefs and other ugliness. For almost all ABIs, 64 bit arguments can
only start in even registers.  Size is now passed to getArgument() so that 32
bit systems can make decisions about register selection for 64 bit arguments.
The number argument is now passed by reference because getArgument() will need
to change it based on the size of the argument and the current argument number.

For ARM, if the argument number is odd and a 64-bit register is requested the
number must first be incremented to because all 64 bit arguments are passed
in an even argument register. Then the number will be incremented again to
access both halves of the argument.
2010-10-01 16:02:46 -05:00
Ali Saidi
b331b02669 ARM: Clean up use of TBit and JBit.
Rather tha constantly using ULL(1) << PcXBitShift define those directly.
Additionally, add some helper functions to further clean up the code.
2010-10-01 16:02:45 -05:00
Ali Saidi
aef4a9904e CPU/Cache: Fix some errors exposed by valgrind 2010-09-30 09:35:19 -05:00
Gabe Black
c41e633e0e X86: Fix the RIP relative versions of the BT, BTC, BTR, and BTS instructions. 2010-09-29 11:31:03 -07:00
Steve Reinhardt
7bae1f5d43 python: get rid of internal.enums package.
Move generated enums into internal.params, which gets
imported into object.params, restoring backward
compatibility for scripts that expect to find them there.
2010-09-22 08:45:35 -07:00
Steve Reinhardt
e918536380 cache: improve coherence handling of writebacks
If we write back an exclusive copy, we now mark it
as such, so the cache receiving the writeback can
mark its copy as exclusive.  This avoids some
unnecessary upgrade requests when a cache later
tries to re-acquire exclusive access to the block.
2010-09-21 23:07:34 -07:00
Gabe Black
ab8d7eee76 CPU: Fix O3 and possible InOrder segfaults in FS. 2010-09-20 02:46:42 -07:00
Steve Reinhardt
3f9f4bf3d6 devices: undo cset 017baf09599f that added timer drain functions.
It's not the right fix for the checkpoint deadlock problem
Brad was having, and creates another bug where the system can
deadlock on restore.  Brad can't reproduce the original bug
right now, so we'll wait until it arises again and then try
to fix it the right way then.
2010-09-16 20:24:05 -07:00
Gabe Black
2dd9f4fcf0 X86: Make the halt microop non-speculative.
Executing this microop makes the CPU halt even if it was misspeculated.
2010-09-14 12:31:37 -07:00
Gabe Black
0bbd88eb40 X86: Make unrecognized instructions behave better in x86. 2010-09-14 12:27:30 -07:00
Gabe Black
0dd1f7f01a CPU: Trim unnecessary includes from some common files.
This reduces the scope of those includes and makes it less likely for there to
be a dependency loop. This also moves the hashing functions associated with
ExtMachInst objects to be with the ExtMachInst definitions and out of
utility.hh.
2010-09-14 00:29:38 -07:00
Gabe Black
8f3fbd2d13 CPU: Get rid of the now unnecessary getInst/setInst family of functions.
This code is no longer needed because of the preceeding change which adds a
StaticInstPtr parameter to the fault's invoke method, obviating the only use
for this pair of functions.
2010-09-13 21:58:34 -07:00
Gabe Black
6833ca7eed Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
2010-09-13 19:26:03 -07:00
Nathan Binkert
2edfcbbaee swig: make all generated files go into the m5.internal package
This is necessary because versions of swig older than 1.3.39 fail to
do the right thing and try to do relative imports for everything (even
with the package= option to %module).  Instead of putting params in
the m5.internal.params package, put params in the m5.internal package
and make all param modules start with param_.  Same thing for
m5.internal.enums.

Also, stop importing all generated params into m5.objects.  They are
not necessary and now with everything using relative imports we wound
up with pollution of the namespace (where builtin-range got overridden).

--HG--
rename : src/python/m5/internal/enums/__init__.py => src/python/m5/internal/enums.py
rename : src/python/m5/internal/params/__init__.py => src/python/m5/internal/params.py
2010-09-12 15:41:34 -07:00
Nathan Binkert
afafaf1dcb style: fix sorting of includes and whitespace in some files 2010-09-10 14:58:04 -07:00
Nathan Binkert
47ef97b9ca scons: Stop building the big monolithic swigged params module
kill params.i and create a separate .i for each object (param, enums, etc.)
2010-09-09 14:26:29 -07:00
Nathan Binkert
e6ee56c657 init: don't build files that centralize python and swig code
Instead of putting all object files into m5/object/__init__.py, interrogate
the importer to find out what should be imported.
Instead of creating a single file that lists all of the embedded python
modules, use static object construction to put those objects onto a list.
Do something similar for embedded swig (C++) code.
2010-09-09 14:15:42 -07:00
Nathan Binkert
710ed8f492 scons: use code_formatter wherever we can in the build system 2010-09-09 14:15:41 -07:00
Nathan Binkert
c514ad9b09 code_formatter: make it easier to insert whitespace
a newline by just doing "code()". indent() and dedent() now take a
"count" parameter to indent/dedent multiple levels.
2010-09-09 14:15:41 -07:00
Nathan Binkert
18ef1bcfa2 swig: don't override SWIG_name anymore
It doesn't appear to be necessary and it is somewhat odd.  I'm pretty
sure that the package parameter to %module does whatever this might
have been before.  It's necessary in future revisions anyway.
2010-09-09 14:15:40 -07:00
Steve Reinhardt
1249728494 cache: fail SC when invalidated while waiting for bus
Corrects an oversight in cset f97b62be544f.  The fix there only
failed queued SCUpgradeReq packets that encountered an
invalidation, which meant that the upgrade had to reach the L2
cache.  To handle pending requests in the L1 we must similarly
fail StoreCondReq packets too.
2010-09-09 14:40:19 -04:00
Steve Reinhardt
6dc599ea9b mem: fix functional accesses to deal with coherence change
We can't just obliviously return the first valid cache block
we find any more... see comments for details.
2010-09-09 14:40:19 -04:00
Steve Reinhardt
71aca6d29e cache: coherence protocol enhancements & bug fixes
Allow lower-level caches (e.g., L2 or L3) to pass exclusive
copies to higher levels (e.g., L1).  This eliminates a lot
of unnecessary upgrade transactions on read-write sequences
to non-shared data.

Also some cleanup of MSHR coherence handling and multiple
bug fixes.
2010-09-09 14:40:18 -04:00
Gabe Black
7c4dc4491a ARM: Get rid of the checkFpEnableFault function in ARM. 2010-08-31 09:50:49 -07:00
Gabe Black
ebf5c5b91b Alpha: Alpha's mt.hh was including mips header files. 2010-08-31 09:48:05 -07:00
Gabe Black
c9d01c6557 CPU: Get rid of the unused ev5_trap function on the simple and checker CPUs. 2010-08-31 09:47:29 -07:00
Gabe Black
794ca517f2 X86: Change the copyright holder to AMD.
I accidentally left myself as a placeholder copyright holder on this file when
I checked it in. Copyright should be assigned to AMD.
2010-08-27 15:35:36 -07:00
Steve Reinhardt
3ffc4505f7 mem: fix m5.fast compile bug in previous cset 2010-08-26 08:03:20 -07:00
Steve Reinhardt
1bf944be62 cache: fix a bug in atomic multilevel snoops 2010-08-25 21:55:55 -07:00
Steve Reinhardt
ee6a92863a memtest: fix/cleanup functional access testing
Don't assert that the response packet is marked as a response
since it won't always be so for functional accesses.

Also cleanup code to refer to functional accesses rather
than "probes" (old terminology), and mention in the
DPRINTF which type of access we're doing.
2010-08-25 21:55:44 -07:00
Ali Saidi
546eaa6109 CPU: Print out traces for faluting inst when the flag ExecFaulting is set 2010-08-25 19:10:43 -05:00
Min Kyu Jeong
dee8f3d500 ARM: Support unaligned memory access.
Without this flag set, page-crossing requests were not split into two mem
request.

Depending on the alignment bit in the SCTLR, misaligned access could
raise a fault. However it seems unnecessary to implement that.
2010-08-25 19:10:43 -05:00
Gene WU
b52fed4747 ARM: Seperate the queues of L1 and L2 walker states. 2010-08-25 19:10:43 -05:00
Min Kyu Jeong
c23e8c31eb ARM: Adding a bogus fault that does nothing.
This fault can used to flush the pipe, not including the faulting instruction.

The particular case I needed this was for a self-modifying code. It needed to
drain the store queue and force the following instruction to refetch from
icache. DCCMVAC cp15 mcr instruction is modified to raise this fault.
2010-08-25 19:10:43 -05:00
William Wang
8376f7bca3 ARM: Remove ALPHA KSeg functions.
These were erronously copied years ago into the ARM directory.
2010-08-25 19:10:43 -05:00
Ali Saidi
c0b54f579c ARM: Limited implementation of dprintk.
Does not work with vfp arguments or arguments passed on the stack.
2010-08-25 19:10:43 -05:00
Min Kyu Jeong
e1168e72ca ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)
When decoding a srs instruction, invalid mode encoding returns invalid instruction.
This can happen when garbage instructions are fetched from mispredicted path
2010-08-25 19:10:43 -05:00
Ali Saidi
edca5f7da6 ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing 2010-08-25 19:10:43 -05:00
Gene WU
4d8f4db8d1 ARM: Use fewer micro-ops for register update loads if possible.
Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
2010-08-25 19:10:42 -05:00
Ali Saidi
c2d5d2b53d ARM: Set the high bits in the part number so it's considered new by some code. 2010-08-25 19:10:42 -05:00
Ali Saidi
99fafb72b8 ARM: Fix VFP enabled checks for mem instructions 2010-08-25 19:10:42 -05:00