cpu/activity.cc:
cpu/activity.hh:
cpu/o3/alpha_cpu.hh:
Updates to include comments.
cpu/base_dyn_inst.cc:
Remove call to thread->misspeculating(), as it's never actually misspeculating.
--HG--
extra : convert_revision : 86574d684770fac9b480475acca048ea418cdac3
The "execute" portion of IEW is really just the last cycle of execution, at which point execute() gets called. Execution begins inside the IQ, when it schedules FUs for specific instructions. As a result, the Execute stage should just pull all completing instructions out of the IQ stage and execute them.
Limiting the number of writebacks outstanding must still be done.
cpu/o3/iew_impl.hh:
Rework how instructions are scheduled and executed. There shouldn't be a specific "width" from issue to execute because issue does the scheduling of the functional units (really the beginning of the execution).
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
Rework how instructions are scheduled and executed.
--HG--
extra : convert_revision : bbf1a8a4c0a2f2a938bdd78d74493048fd3b4b55
IsIprAccess flag may go away in the future (op class can be used to tell this), and the CPU still needs a specific way to identify/deal with syscalls.
arch/alpha/isa/decoder.isa:
Added a few extra flags to help the new CPU identify various classes of instructions without having to force certain behaviors for all CPUs.
cpu/base_dyn_inst.hh:
cpu/static_inst.hh:
Added extra flags.
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue_impl.hh:
Handle store conditionals specially.
cpu/o3/lsq_unit_impl.hh:
Extra flags tells if the instruction is a store conditional.
cpu/o3/rename_impl.hh:
Handle IPR accesses and store conditionals specially.
--HG--
extra : convert_revision : 39debec4fa5341ae8a8ab5650bd12730aeb6c04f
Dependecy graph code moved into its own class.
This requires the changes to the functional units, which is in the next check in.
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
IEW and IQ code cleanup and reorganization.
cpu/o3/inst_queue.cc:
Dependency graph code moved into its own class now.
cpu/o3/inst_queue.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
cpu/o3/inst_queue_impl.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
Issue loop cleaned up, with completion events for functional units now used more correctly (before they weren't used for multi-cycle ops with pipelined FU's).
--HG--
extra : convert_revision : 35e50192df6f71dc81d46a73fdd65f7ec07c10e4
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
fixup for bsd hosts. Some headers are included by default which means that
more variables need TGT_ prefixes and there isn't a stat call (everything
is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
I much cleaner way to get max int
sim/syscall_emul.hh:
fix stat64 problems on *BSD
--HG--
extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942
