Commit graph

557 commits

Author SHA1 Message Date
Gabe Black
fd77212b72 Add code to generate register and immediate based integer op microop classes.
--HG--
extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
2007-03-29 00:49:53 -07:00
Gabe Black
276f6d794d Add a junk operand. With no operands, the parser breaks.
--HG--
extra : convert_revision : 7410fd3681ed3d9b1293d982ed5f3553a6c75f3f
2007-03-21 21:09:24 +00:00
Gabe Black
bbffaa8ee0 Start implementing groups of instructions which do the same thing on different sets of inputs.
--HG--
extra : convert_revision : 6a5be61831588f801965dd4e80cb52f28911c320
2007-03-21 21:07:43 +00:00
Gabe Black
0a80d06dea Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are.
--HG--
extra : convert_revision : 8768676eac25e6a4f0dc50ce2dc576bdcdd6e025
2007-03-21 19:19:53 +00:00
Gabe Black
3efec59fc5 Missed a const
--HG--
rename : src/arch/x86/isa/decoder.isa => src/arch/x86/isa/decoder/decoder.isa
extra : convert_revision : a60e7495da6fe99fa2375a3f801f2962c3e41adb
2007-03-21 19:15:40 +00:00
Gabe Black
a2b56088fb Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.
src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
    Make the predecoder an object with it's own switched header file.

--HG--
extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
2007-03-15 02:47:42 +00:00
Gabe Black
a41b86ba01 Stub decoder. This is probably even farther from finished than it looks...
--HG--
extra : convert_revision : a39a158fec4560f6eb7a6987592c473677c0b1ba
2007-03-05 16:16:28 +00:00