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Author SHA1 Message Date
Gabe Black
6ebce9d65a Alpha: Phase out Alpha's intregfile.hh and intregfile.cc. 2009-07-08 23:02:21 -07:00
Gabe Black
faa6ebebe1 SPARC: Phase out SPARC's intregfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black
ecde884404 X86: Phase out x86's intregfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black
301df68c73 MIPS: Phase out MIPS's int_regfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black
27b6148f47 ARM: Flush out the ARM's int_regfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black
a480ba00b9 Registers: Eliminate the ISA defined integer register file. 2009-07-08 23:02:20 -07:00
Gabe Black
0cb180ea0d Registers: Eliminate the ISA defined floating point register file. 2009-07-08 23:02:20 -07:00
Gabe Black
25884a8773 Registers: Get rid of the float register width parameter. 2009-07-08 23:02:20 -07:00
Gabe Black
32daf6fc3f Registers: Add an ISA object which replaces the MiscRegFile. 
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
 2009-07-08 23:02:20 -07:00
Gabe Black
3e2cad8370 ARM: Use custom read/write code to alias R15 with the PC. 2009-07-08 23:02:20 -07:00
Gabe Black
b8b7c7314a ISA parser: Allow alternative read/write code for operands. 2009-07-08 23:02:19 -07:00
Gabe Black
95392d3fb8 ARM: Move the remaining microops out of the decoder and into the ISA desc. 2009-07-08 23:02:19 -07:00
Gabe Black
1d4f338b39 ARM: Move the memory microops out of the decoder and into the ISA desc. 2009-07-08 23:02:19 -07:00
Gabe Black
70a75ceb84 ARM: Move the integer microops out of the decoder and into the ISA desc. 2009-07-08 23:02:19 -07:00
Gabe Black
4eb18cc07a ARM: Improve memory instruction disassembly. 2009-07-08 23:02:19 -07:00
Gabe Black
2fb8d481ab ARM: Tune up predicated instruction decoding. 2009-07-08 23:02:19 -07:00
Gabe Black
ddcf084f16 ARM: Get rid of the MemAcc and EAComp static insts. 2009-07-08 23:02:19 -07:00
Gabe Black
cae870eded ARM: Get rid of end_addr in the ArmMacroStore constructor. 2009-07-08 23:02:19 -07:00
Gabe Black
311f77f33d ARM: Add an AddrMode2 format for memory instructions that use address mode 2. 2009-07-08 23:02:19 -07:00
Gabe Black
826a3582ea ARM: Don't always update CPSR. 2009-07-08 23:02:19 -07:00
Gabe Black
17f0943398 ARM: Add an AddrMode3 format for memory instructions that use address mode 3. 2009-07-08 23:02:19 -07:00
Gabe Black
dac0cb5c7e ARM: Add load/store double instructions. 2009-07-08 23:02:10 -07:00
Gabe Black
1ca0688c4c ARM: Add operands for the load/store double instructions. 2009-07-08 23:02:01 -07:00
Gabe Black
d029110fa1 X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was intended. 2009-07-08 23:01:54 -07:00
Derek Hower
15afc87f7c slicc: fixed MI_example bug. The directory wasn't deallocating the TBE, leading to a leak. Also increased the default max TBE size to 256 to allow memtest to pass the regression. 2009-07-08 08:40:32 -05:00
Derek Hower
6a83bd5a03 ruby: set the default values of the debug object so that nothing is printed 2009-07-08 00:34:40 -05:00
Derek Hower
2f9d8bff5b slicc: Fixed MI_example bug. The directory was not writing data to DRAM after a PUTX. 2009-07-08 00:31:33 -05:00
Derek Hower
96c36afea9 removed stray debug print 2009-07-07 23:01:35 -05:00
Nathan Binkert
7ffb8e5914 automerge 2009-07-06 15:54:18 -07:00
Nathan Binkert
da704f52e5 ruby: Fix RubyMemory to work with the newer ruby. 2009-07-06 15:49:47 -07:00
Nathan Binkert
a7904e2cf3 ruby: apply some fixes that were overwritten by the recent ruby import. 2009-07-06 15:49:47 -07:00
Nathan Binkert
5b080ae046 slicc: update parser.py for changes in slicc language. 2009-07-06 15:49:47 -07:00
Nathan Binkert
1f6933503d scons: update SCons files for changes in ruby. 2009-07-06 15:49:47 -07:00
Nathan Binkert
92de70b69a ruby: Import the latest ruby changes from gems. 
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it.  One known regression
is that atomic memory operations do not seem to work properly anymore.
 2009-07-06 15:49:47 -07:00
Nathan Binkert
05f6a4a6b9 ruby: replace strings that were missed in original ruby import. 2009-07-06 15:49:47 -07:00
Gabe Black
240e214236 SPARC: Fix the parenthesis in inUserMode. 2009-07-05 16:07:09 -07:00
Jack Whitham
a223a065e6 ARM: Fix how address mode bits are handled. 2009-07-02 23:23:06 -07:00
Jack Whitham
a738006397 ARM: Fix the code snippet for mla. 2009-07-02 23:22:58 -07:00
Nathan Binkert
7daed385bf typo: correct spelling 2009-07-02 16:48:22 -07:00
Nathan Binkert
6fd3987b3f attrdict: correct delattr 2009-07-02 16:48:22 -07:00
Gabe Black
26c70ce2cb ARM: Make DataOps select from a set of ways to set the c and v flags. 2009-07-01 22:17:06 -07:00
Gabe Black
148c265cf3 ARM: Get rid of some bitfields that aren't used. A few may need to be readded. 2009-07-01 22:16:51 -07:00
Gabe Black
7172e26cc4 ARM: Add a findLsbSet function and use it to implement clz. 2009-07-01 22:16:36 -07:00
Gabe Black
f5141c23fd ARM: Add defaults for DataOp flag code. 2009-07-01 22:16:19 -07:00
Gabe Black
22a1ac22f4 ARM: Get rid of the val2 variable. 2009-07-01 22:16:05 -07:00
Gabe Black
ce9cb1ecb5 ARM: Centralize the declaration of resTemp. 2009-07-01 22:15:39 -07:00
Gabe Black
776a06fd39 ARM: Add a DataImmOp format similar to DataOp. 2009-07-01 22:12:10 -07:00
Gabe Black
4f98171479 ARM: Decode some media instructions. These are untested. 2009-07-01 22:11:54 -07:00
Gabe Black
b8f064c88c ARM: Use the new DataOp format to simplify the decoder. 2009-07-01 22:11:39 -07:00
Gabe Black
f409d7819d ARM: Add in some new artificial fields that make decoding a little easier. 2009-07-01 22:11:27 -07:00
Gabe Black
1f0c0a6688 ARM: Recognize the IntRegs trace flag. 2009-07-01 22:11:12 -07:00
Gabe Black
065cb59427 ARM: Add a DataOp format so data op definitions can be aggregated. 2009-07-01 22:10:58 -07:00
Gabe Black
1ea14b8fac ARM: Show more information when disassembling data processing intstructions. 
This will need more work, but it should be a lot closer.
 2009-06-27 00:30:23 -07:00
Gabe Black
56f1845471 ARM: Show branch targets relative to the nearest symbol. 2009-06-27 00:29:30 -07:00
Gabe Black
a4ac3fad7a ARM: Write a function for printing mnemonics and predicates. 2009-06-27 00:29:12 -07:00
Gabe Black
38d8bc64ba ARM: Fill out the printReg function. 2009-06-26 22:01:34 -07:00
Jack Whitman
7b5386d390 ARM: Fix signed multiply long and add some unimplemented loads. 2009-06-24 21:22:52 -07:00
Jack Whitman
853a0858f3 ARM: Link register is trashed by non-executed branch and link operations. 2009-06-24 21:22:46 -07:00
Jack Whitman
6dd4272804 ARM: Added unimplemented load/store multiple instructions. 2009-06-23 23:23:25 -07:00
Gabe Black
d744525273 ARM: Simplify some utility functions. 2009-06-21 22:51:13 -07:00
Gabe Black
5c2a362cb7 ARM: Move util functions out of the isa desc. 2009-06-21 22:50:33 -07:00
Gabe Black
d4a03f1900 ARM: Simplify the ISA desc by pulling some classes out of it. 2009-06-21 17:21:25 -07:00
Gabe Black
2a39570b78 ARM: Remove the currently unecessary FPAOp class. 2009-06-21 17:14:51 -07:00
Gabe Black
d1d733f636 ARM: Make inst bitfields accessible outside of the isa desc. 2009-06-21 16:41:21 -07:00
Gabe Black
47e71d674a ARM: Don't downconvert ExtMachInsts to MachInsts. 2009-06-21 16:41:07 -07:00
Gabe Black
f1657a890e BitUnion: Add more constiness. 2009-06-21 16:40:33 -07:00
Gabe Black
7e4f132369 ARM: Get rid of a few more unused operands. 2009-06-21 09:48:51 -07:00
Gabe Black
4415e2dcd6 ARM: Get rid of unnecessary Re operand. 2009-06-21 09:48:44 -07:00
Gabe Black
7d4ef8a398 ARM: Clear out some inherited hangers on in util.isa and utility.hh. 2009-06-21 09:43:55 -07:00
Gabe Black
5bc1373050 ARM: Get rid of unnecessary fp_enable_checks. 2009-06-21 09:41:04 -07:00
Gabe Black
3964709711 ARM: Adjust simplify rotate_imm slightly. 2009-06-21 09:38:54 -07:00
Gabe Black
c20ce20e4c ARM: Make the isa parser aware that CPSR is being used. 2009-06-21 09:37:41 -07:00
Gabe Black
71e0d1ded2 ARM: Pull some static code out of the isa desc and create miscregs.hh. 2009-06-21 09:21:07 -07:00
Gabe Black
19a1966079 ARM: Get rid of unused postacc_code. 2009-06-21 09:16:55 -07:00
Nathan Binkert
e1eacc8d92 scons: Make shared library builds work again 
Compile gzstream as position independent code
use the PIC version of date for shared libs...oops
 2009-06-12 21:19:16 -07:00
Nathan Binkert
d3d8a5a83b copyright: I missed some copyrights during ruby integration 2009-06-10 00:41:56 -07:00
Gabe Black
b394242240 ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall params. 2009-06-09 23:41:45 -07:00
Gabe Black
c913c64be2 ARM: Add a memory_barrier function to the "comm page". 
This function doesn't actually provide a memory barrier (I don't think they're
implemented) and instead just returns.
 2009-06-09 23:41:35 -07:00
Gabe Black
3ff1e922c2 ARM: Add a cmpxchg implementation to the "comm page". 
This implementation does what it's supposed to (I think), but it's not atomic
and doesn't have memory barriers like the kernel's version.
 2009-06-09 23:41:03 -07:00
Gabe Black
37ac2871d5 ARM: Implement TLS. This is not tested. 2009-06-09 23:39:07 -07:00
Gabe Black
5daeefc505 ARM: Make ArmLinuxProcess understand "ARM private" system calls. 2009-06-09 23:38:50 -07:00
Gabe Black
fbf4dc9da2 ARM: Update the kernel version M5 reports to 2.6.16.19 2009-06-09 23:37:41 -07:00
Nathan Binkert
baa0d695b2 cleanup: Make use of types properly and make the loop a little more clear. 2009-06-05 17:01:19 -07:00
Nathan Binkert
c76a8b1c15 scons: Make it so that the processing of trace flags does not depend on order 2009-06-05 15:20:09 -07:00
Nathan Binkert
a01437ab03 types: need typename keyword to get the type. 2009-06-05 11:40:02 -07:00
Nathan Binkert
6faf377b53 types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
Nathan Binkert
4e34266245 move: put predictor includes and cc files into the same place 
--HG--
rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc
rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh
rename : src/cpu/btb.cc => src/cpu/pred/btb.cc
rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh
rename : src/cpu/ras.cc => src/cpu/pred/ras.cc
rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh
rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc
rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh
 2009-06-04 21:50:20 -07:00
Nathan Binkert
e30c62ad99 style: cleanup style 2009-06-04 21:41:46 -07:00
Nathan Binkert
b08c361911 swig: %include Event before PythonEvent so python gets the subclass correct. 
Before this change, some versions of swig would cause PythonEvent to be
derived from object instead of Event
 2009-06-01 16:38:57 -07:00
Nathan Binkert
a0104b6ff6 request: add accessor and constructor for setting time other than curTick 2009-05-29 15:30:16 -07:00
Gabe Black
7f50ea05ac X86: Keep track of more descriptor state to accomodate KVM. 2009-05-28 23:27:56 -07:00
Nathan Binkert
47877cf2db types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
Gabe Black
d93392df28 X86: Really set up the GDT and various hidden/visible segment registers. 2009-05-26 02:23:08 -07:00
Steve Reinhardt
b3d0a01eb3 igbe: Fix descriptor cache bug. 2009-05-20 21:52:32 -07:00
Nathan Binkert
8d2e51c7f5 includes: sort includes again 2009-05-17 14:34:52 -07:00
Nathan Binkert
709d859530 includes: use base/types.hh not inttypes.h or stdint.h 2009-05-17 14:34:51 -07:00
Nathan Binkert
eef3a2e142 types: Move stuff for global types into src/base/types.hh 
--HG--
rename : src/sim/host.hh => src/base/types.hh
 2009-05-17 14:34:50 -07:00
Nathan Binkert
cbf237897f stats: tidy up the Distribution type a little bit 2009-05-13 07:18:03 -07:00
Nathan Binkert
cfa9c78100 stats: fancy is a bad name 2009-05-13 07:18:02 -07:00
Nathan Binkert
74c595d739 stats: clean up the code for printing stats 2009-05-13 07:18:01 -07:00
Korey Sewell
97a04b16eb mips-merge: merge hello world regress for inorder cpu 
w/latest changes
 2009-05-13 02:02:05 -04:00
Nathan Binkert
5207586b26 ruby: deal with printf warnings and convert some to cprintf 2009-05-12 22:33:05 -07:00
Nathan Binkert
016d472c46 ruby: remove random uint typedef and use unsigned 2009-05-12 22:33:05 -07:00
Nathan Binkert
7389dc63b2 ruby: Make ruby's Map use hashmap.hh to simplify things. 2009-05-12 22:33:05 -07:00
Nathan Binkert
82c9e6a5fc gcc: work around a bogus gcc error 2009-05-12 22:33:05 -07:00
Nathan Binkert
0c2b9cf90d slicc: work around improper initialization of a global in slicc. 2009-05-12 22:33:05 -07:00
Nathan Binkert
d923ce0f8c slicc: clean up the slicc environment so things build properly on mac. 2009-05-12 22:33:04 -07:00
Korey Sewell
1f4c954590 inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp 
Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change
to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU
 2009-05-13 01:26:46 -04:00
Korey Sewell
bc69e7947c arch-mips: add regWidth constant to float regfile 2009-05-13 01:26:38 -04:00
Korey Sewell
a032d91016 cpus: add InOrderCPU to default build 
regressions need this so they build the model
 2009-05-12 20:55:21 -04:00
Korey Sewell
5d810c30e6 alpha-isa: add mt.hh so it can compile with inorder 2009-05-12 20:18:34 -04:00
Korey Sewell
6c88730540 inorder-resources: delete events 
make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
 2009-05-12 15:01:16 -04:00
Korey Sewell
db2b721380 inorder-tlb-cunit: merge the TLB as implicit to any memory access 
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
 2009-05-12 15:01:16 -04:00
Korey Sewell
3a057bdbb1 inorder-tlb: squash insts in TLB correctly 
TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly
* * *
 2009-05-12 15:01:16 -04:00
Korey Sewell
f1c97e830b inorder-faults: ignore unalign translation faults for prefetches 2009-05-12 15:01:16 -04:00
Korey Sewell
fe4cd9847d inorder-stc: update interface to handle store conditionals 2009-05-12 15:01:15 -04:00
Korey Sewell
6211fe5d2e inorder-float: Fix storage of FP results 
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access
because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from
the actual floating point register file, the model can figure out what it needs to store
 2009-05-12 15:01:15 -04:00
Korey Sewell
3603dd25ef inorder-fetch: update model to use predecoder 2009-05-12 15:01:15 -04:00
Korey Sewell
c9a03f549b inorder-mem: clean up allocation/deletion of requests/packets 
* * *
 2009-05-12 15:01:15 -04:00
Korey Sewell
1c7e988272 inorder-mem: skeleton support for prefetch/writehints 2009-05-12 15:01:15 -04:00
Korey Sewell
f41df0ee08 inorder-o3: allow both to compile together 
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
 2009-05-12 15:01:14 -04:00
Korey Sewell
5127ea226a inorder-unified-tlb: use unified TLB instead of old TLB model 2009-05-12 15:01:14 -04:00
Korey Sewell
98b1452058 inorder-miscregs: Fix indexing for misc. reg operands and update result-types for better tracing of these types of values 2009-05-12 15:01:14 -04:00
Korey Sewell
2012202b06 inorder/alpha-isa: create eaComp object visible to StaticInst through ISA 
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
 2009-05-12 15:01:14 -04:00
Korey Sewell
b569f8f0ed inorder-bpred: edits to handle non-delay-slot ISAs 
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
 2009-05-12 15:01:14 -04:00
Korey Sewell
1c8dfd9254 inorder-alpha-port: initial inorder support of ALPHA 
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
 2009-05-12 15:01:13 -04:00
Korey Sewell
63db33c4b1 isa-parser: made a few changes, but not author-worthy 2009-05-12 15:01:13 -04:00
Nathan Binkert
f21e80ec72 ruby: assert(false) should be panic. 
This also fixes some compiler warnings
 2009-05-11 16:32:32 -07:00
Nathan Binkert
c2c68c66b7 stats: remove a few compat leftovers 2009-05-11 11:18:09 -07:00
Nathan Binkert
20f1da8b96 python: pull out common code from main that processes arguments 2009-05-11 11:18:09 -07:00
Nathan Binkert
5de3b2b6f0 stats: forgot an include for the mysql stuff 2009-05-11 11:18:09 -07:00
Nathan Binkert
5b752c1e31 scons: add include guards to info.hh 2009-05-11 11:18:09 -07:00
Nathan Binkert
cf6b4ef734 ruby: add RUBY sticky option that must be set to add ruby to the build 
Default is false
 2009-05-11 10:38:46 -07:00
Daniel Sanchez
93f2f69657 ruby: Working M5 interface and updated Ruby interface. 
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5.  Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
  tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
 2009-05-11 10:38:46 -07:00
Steve Reinhardt
ebf2f5aadd ruby: Check stderr and not stdin before hanging on an assert. 2009-05-11 10:38:46 -07:00
Polina Dudnik
7769cc9092 ruby: decommission code 
1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.*
2. Decomissioned all bloom filters
3. Decomissioned ruby/simics directory
 2009-05-11 10:38:46 -07:00
Derek Hower
0ccf8f35a5 ruby: removed dead functions from the sequencer 2009-05-11 10:38:46 -07:00
Polina Dudnik
29f82f265a ruby: Removed g_SIMULATING flag 
1. removed checks from tester files
2. removed else clause in Sequencer and DirectoryMemory else clause is
needed by the tester, it is up to Derek to revive it elsewhere when he
gets to it

Also:
1. Changed m_entries in DirectoryMemory to a map
2. And replaced SIMICS_read_physical_memory with a call to now-dummy
Derek's-to-be readPhysMem function
 2009-05-11 10:38:46 -07:00
Polina Dudnik
b271090923 ruby: Remove transactional access types (e.g. LD_XACT) from CacheRequestType 
1. Modified enumeration
2. Also modified profiler
3. Remove transactions from Tester
4. Edited XACT_MEM out of Synthetic Driver
 2009-05-11 10:38:46 -07:00
Polina Dudnik
9f34659c52 ruby: reordered Debug and RubyConfig::init to fix segfault 
due to uninitialized output file pointer.
 2009-05-11 10:38:46 -07:00
Dan Gibson
8cbf8df5b7 ruby: Disabled RubyEventQueue's deletion of its home-grown priority heap. 
Temporarily to fix unusual memory problem.
 2009-05-11 10:38:46 -07:00
Nathan Binkert
7311fd7182 ruby: Migrate all of ruby and slicc to SCons. 
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use.  This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time.  The easiest thing wound up being
to write a parser for slicc that would tell me.  Incidentally this
means we now have a slicc grammar written in python.
 2009-05-11 10:38:46 -07:00
Nathan Binkert
e40b8e34c8 ruby: clean up a few warnings 2009-05-11 10:38:45 -07:00
Dan Gibson
8b9f70b9e4 ruby: Fixed some unresolved references. 2009-05-11 10:38:45 -07:00
Nathan Binkert
24da30e317 ruby: Make ruby #includes use full paths to the files they're including. 
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths.  Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
 2009-05-11 10:38:45 -07:00
Dan Gibson
d8c592a05d ruby: remove unnecessary code. 
1) Removing files from the ruby build left some unresovled
symbols. Those have been fixed.

2) Most of the dependencies on Simics data types and the simics
interface files have been removed.

3) Almost all mention of opal is gone.

4) Huge chunks of LogTM are now gone.

5) Handling 1-4 left ~hundreds of unresolved references, which were
fixed, yielding a snowball effect (and the massive size of this
delta).
 2009-05-11 10:38:45 -07:00
Derek Hower
6ceaffd724 ruby: Cleaned up sequencer. Removed LogTM specific code. 2009-05-11 10:38:45 -07:00
Derek Hower
3d2acc547c ruby: added Packet interface to makeRequest and isReady. 
Also pushed Packet usage into the Sequencer
 2009-05-11 10:38:45 -07:00
Nathan Binkert
e1915f16d1 ruby: fold the debugging options into Debug.cc 2009-05-11 10:38:45 -07:00
Derek Hower
6e8373fad6 ruby: Renamed Ruby's EventQueue to RubyEventQueue 
--HG--
rename : src/mem/ruby/eventqueue/EventQueue.cc => src/mem/ruby/eventqueue/RubyEventQueue.cc
rename : src/mem/ruby/eventqueue/EventQueue.hh => src/mem/ruby/eventqueue/RubyEventQueue.hh
rename : src/mem/ruby/eventqueue/EventQueueNode.cc => src/mem/ruby/eventqueue/RubyEventQueueNode.cc
rename : src/mem/ruby/eventqueue/EventQueueNode.hh => src/mem/ruby/eventqueue/RubyEventQueueNode.hh
 2009-05-11 10:38:45 -07:00