2 commits

Author	SHA1	Message	Date
Korey Sewell	f69b018571	make handling of interstage buffers (i.e. StageQueues) more consistent: (1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads	2009-03-04 13:17:07 -05:00
Korey Sewell	973d8b8b13	InOrder: Import new inorder CPU model from MIPS. ... This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen!	2009-02-10 15:49:29 -08:00