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2 commits

Author SHA1 Message Date
Steve Reinhardt 935ba67b4f Get basic full-system working with AtomicSimpleCPU.
SConscript:
    Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
    Fix paths.
configs/test/fs.py:
    SimpleCPU -> AtomicSimpleCPU
    Fix vmlinux path
cpu/simple/atomic.cc:
    Fix suspendContext() so quiesce works.
    Don't forget to checkForInterrupts().
cpu/simple/base.cc:
    Minor fix to interrupt check code.
dev/ide_disk.hh:
    Don't declare regStats() in header since it's not in
    .cc file anymore (will need to add it back in when
    stats are added back).
dev/io_device.cc:
    Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
    Set PCI config packet result to Success.
python/m5/objects/Root.py:
    Add debug object to Root so things like break_cycles
    can be set from command line.

--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
2006-05-17 22:08:44 -04:00
Ali Saidi 8f8d09538f Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working
after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-24 19:31:50 -04:00