sanchayanmaity/gem5
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14 commits

Author SHA1 Message Date
Erik Hallnor
6610699987 Add COW support to the IIC. 
cpu/memtest/memtest.cc:
    Move the trace Addr to the end of the printouts

--HG--
extra : convert_revision : 875f0a3f65e07f531a23fea6be07fbf3239ec2c4
 2004-02-17 22:53:15 -05:00
Erik Hallnor
7fd91f7c4c Add full copy support. 
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
    Add 2 new parameters to control the percentage of unaligned copy sources and destinations.

--HG--
extra : convert_revision : 2646ee2f195e9f3e76bc257b8716163ef63a9f40
 2004-02-14 03:25:39 -05:00
Erik Hallnor
14c11155be Add support for multiple outstanding aligned copies 
cpu/memtest/memtest.cc:
    Add traceBlockAddr to trace outputs.

--HG--
extra : convert_revision : e4ebaf9647fb393448367f4f4af3bae566f51c24
 2004-02-10 20:37:38 -05:00
Erik Hallnor
f0abedf769 Add LRU aligned copies to the hierarchy, with only one outstanding copy. Aligned copies now fully work in LRU (just need to write the IIC doCopy call). At the moment they are slow since a stalled copy stalls the entire cache. 
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
    Add aligned copy tests, percent of copies is specified by percent_copies

--HG--
extra : convert_revision : eaf1900fcb8832db98249e94e3472ebfb049eb48
 2004-02-09 17:37:27 -05:00
Steve Reinhardt
7b07b0877f Change MemReqPtr parameters to references. 
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
    Change MemReqPtr parameters to references.

--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
 2004-02-02 10:47:21 -08:00
Steve Reinhardt
1cb7159966 Make memtest compile again. 
cpu/memtest/memtest.hh:
    Oops... make memtest compile with new event priorities too.

--HG--
extra : convert_revision : 8143f2e078bb785991d351803fc3a6a50aa31ae5
 2003-12-11 08:46:21 -08:00
Erik Hallnor
aead4c315b Various fixes to memory code. 
cpu/memtest/memtest.cc:
    Disable probes until the work in all cases
util/rundiff:
    Comment out Algorithm::Diff since its not needed.

--HG--
extra : convert_revision : 40e76ae8926650986a170a0ba6ef331519aceb19
 2003-11-06 18:39:26 -05:00
Erik Hallnor
26ababf2f2 Probe is now in. You currently can't probe uncacheable (of course it doesn't make much sense either. 
Also, probe doesn't currently support compressed data, but will as soon as I encapsulate the calls more.

cpu/memtest/memtest.cc:
    Change memtest to not do probes on uncacheables.

--HG--
extra : convert_revision : 28ca4f793562e55da75e8b7fc3852bb5b1328ea9
 2003-10-22 00:22:25 -04:00
Erik Hallnor
f3d6ac18e8 Merge ehallnor@zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/ehallnor/m5 
--HG--
extra : convert_revision : 1fcdbd9d2efc1e0490716de46c81e94f4b28678b
 2003-10-21 01:53:41 -04:00
Erik Hallnor
456b9af0c8 memtest.cc: 
Add probe calls to test update probe path.

cpu/memtest/memtest.cc:
    Add probe calls to test update probe path.

--HG--
extra : convert_revision : b0fb97b54b6ffce9c575fda680b778da63767b7c
 2003-10-21 01:53:27 -04:00
Nathan Binkert
e0b065ff7c Separate the stuff for SimObject from SimObject builder. 
This makes testing a bit easier.

arch/alpha/alpha_memory.cc:
cpu/intr_control.cc:
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/alpha_console.cc:
dev/console.cc:
dev/disk_image.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ethertap.cc:
dev/simple_disk.cc:
kern/tru64/tru64_system.cc:
sim/main.cc:
sim/prog.cc:
    Need to include builder.hh
    sort #includes
sim/sim_object.cc:
sim/sim_object.hh:
    Separate the SimObjectBuilder stuff into its own file

--HG--
extra : convert_revision : e8395e0cc6ae1f180f9cd6f100795a1ac44aeed5
 2003-10-20 20:17:01 -04:00
Erik Hallnor
4134477369 Add a commited loads event queue similar to the one for commited instructions. 
Two new parameters for the CPU models, max_loads_any_thread and max_loads_all_threads.

cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
    Swap out maxReads for the new commited loads model.

--HG--
extra : convert_revision : 35031329bbc476122b2203104537a9f8b46addfa
 2003-10-16 17:04:18 -04:00
Steve Reinhardt
25693e9e69 Make include paths explicit and update makefile accordingly. 
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/faults.cc:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/circlebuf.cc:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/cprintf.cc:
base/cprintf.hh:
base/fast_alloc.cc:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/exec_aout.h:
base/loader/exec_ecoff.h:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/misc.cc:
base/misc.hh:
base/pollevent.cc:
base/pollevent.hh:
base/random.cc:
base/random.hh:
base/range.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/trace.cc:
base/trace.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/prog.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/sim_time.cc:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/tap/tap.cc:
    Make include paths explicit.

--HG--
extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
 2003-10-10 11:09:00 -07:00
Steve Reinhardt
52b31ea0a6 File moves for the reorg. Tree is in broken state until I commit the makefile and 
#include changes.

--HG--
rename : sim/cache/lzss_compression.cc => base/compression/lzss_compression.cc
rename : sim/cache/lzss_compression.hh => base/compression/lzss_compression.hh
rename : sim/cache/null_compression.hh => base/compression/null_compression.hh
rename : sim/hybrid_pred.cc => base/hybrid_pred.cc
rename : sim/hybrid_pred.hh => base/hybrid_pred.hh
rename : base/aout_object.cc => base/loader/aout_object.cc
rename : base/aout_object.hh => base/loader/aout_object.hh
rename : base/coff_sym.h => base/loader/coff_sym.h
rename : base/coff_symconst.h => base/loader/coff_symconst.h
rename : base/ecoff_object.cc => base/loader/ecoff_object.cc
rename : base/ecoff_object.hh => base/loader/ecoff_object.hh
rename : base/elf_object.cc => base/loader/elf_object.cc
rename : base/elf_object.hh => base/loader/elf_object.hh
rename : base/exec_aout.h => base/loader/exec_aout.h
rename : base/exec_ecoff.h => base/loader/exec_ecoff.h
rename : base/object_file.cc => base/loader/object_file.cc
rename : base/object_file.hh => base/loader/object_file.hh
rename : base/symtab.cc => base/loader/symtab.cc
rename : base/symtab.hh => base/loader/symtab.hh
rename : sim/predictor.hh => base/predictor.hh
rename : sim/sat_counter.cc => base/sat_counter.cc
rename : sim/sat_counter.hh => base/sat_counter.hh
rename : sim/base_cpu.cc => cpu/base_cpu.cc
rename : sim/base_cpu.hh => cpu/base_cpu.hh
rename : sim/exec_context.cc => cpu/exec_context.cc
rename : sim/exec_context.hh => cpu/exec_context.hh
rename : sim/exetrace.cc => cpu/exetrace.cc
rename : sim/exetrace.hh => cpu/exetrace.hh
rename : sim/op_class.hh => cpu/full_cpu/op_class.hh
rename : sim/smt.hh => cpu/full_cpu/smt.hh
rename : sim/inst_seq.hh => cpu/inst_seq.hh
rename : sim/intr_control.cc => cpu/intr_control.cc
rename : sim/intr_control.hh => cpu/intr_control.hh
rename : sim/memtest.cc => cpu/memtest/memtest.cc
rename : sim/memtest.hh => cpu/memtest/memtest.hh
rename : sim/pc_event.cc => cpu/pc_event.cc
rename : sim/pc_event.hh => cpu/pc_event.hh
rename : sim/simple_cpu.cc => cpu/simple_cpu/simple_cpu.cc
rename : sim/simple_cpu.hh => cpu/simple_cpu/simple_cpu.hh
rename : sim/static_inst.cc => cpu/static_inst.cc
rename : sim/static_inst.hh => cpu/static_inst.hh
extra : convert_revision : 05bd41acb2a424f1a38609fd4ac6df681bb479d6
 2003-10-10 09:57:26 -07:00