Commit graph

1081 commits

Author SHA1 Message Date
Lisa Hsu
01c959aeaf Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
2007-01-19 21:34:21 -05:00
Lisa Hsu
f1aeaf7ceb some hstick and hintp changes.
src/arch/sparc/interrupts.hh:
    condition hstick matches on HINTP
src/arch/sparc/miscregfile.cc:
    implement HINTP
src/arch/sparc/ua2005.cc:
    don't post interrupt unless it is enabled.

--HG--
extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
2007-01-19 21:33:36 -05:00
Ali Saidi
ae0d8d1681 Allow ASI_LDTX_REAL
--HG--
extra : convert_revision : ba1af012ab8ac61a25058977cb7ec511eb2cf3cb
2007-01-17 18:36:12 -05:00
Ali Saidi
c8a2d602b1 do a linear search for matching tlb entries instead of using map because you could be mapping a larger page that intersects many
fix for lookup table to keep it consistant with tlb on a replace of a specific entry

--HG--
extra : convert_revision : 5a14fbcdcfc13156c63fa41ddeca474660143b32
2007-01-17 17:59:22 -05:00
Ali Saidi
8173a05eaf Implement reading writing of sync fault status register and address register
--HG--
extra : convert_revision : c2f60e49683446bcc3afdf911da172de0422b8ad
2007-01-17 13:09:26 -05:00
Ali Saidi
64528df38d In the case that we generate a fault (e.g. a tlb miss) on a microcoded instruction set curMacroStaticInst to null
This way we'll jump immediately to the handler

--HG--
extra : convert_revision : 36218d3a5c2342337e66e1229ea2219533efd41e
2007-01-16 19:12:33 -05:00
Ali Saidi
8d75e4ac3f Don't add symbols for loaded files to symbol table since they are pretty much meaningless with all the copying that goes on
--HG--
extra : convert_revision : 4d2c1bb72c0344d78d9c3d5958feb3de247102a0
2007-01-16 19:09:27 -05:00
Ali Saidi
d6c92cdb3c Fix legion lock code a bit so that if we jump out of a micro coded instruction (because of a fault on the first op) we don't lose sync with legion
Only print TLB if there is a tlb difference

--HG--
extra : convert_revision : f3baf667ca466d6b8efcaccd186ecec14498229d
2007-01-16 19:08:21 -05:00
Ali Saidi
0584d5bd6c In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks
--HG--
extra : convert_revision : e7b21c56eadf4603ab03364741b00c9689492423
2007-01-16 19:06:33 -05:00
Ali Saidi
ecfd628ecd Modify ISA and staticInst to support a IsFirstMicroOp flag
Increment instruction count on first micro-op instead of last

src/arch/sparc/isa/decoder.isa:
    Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
    set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
    Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
    Add IsFirstMicroop flag to static insts

--HG--
extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
2007-01-16 19:06:05 -05:00
Lisa Hsu
5c9cbdbb45 Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge between ali and me.

--HG--
extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
2007-01-11 09:48:15 -05:00
Lisa Hsu
42535f5f53 ua2005.cc:
formatting/indentation for case statements

src/arch/sparc/ua2005.cc:
    formatting/indentation for case statements

--HG--
extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
2007-01-11 09:41:34 -05:00
Lisa Hsu
9f75c1c58f ua2005.cc:
i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

src/arch/sparc/ua2005.cc:
    i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

--HG--
extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
2007-01-11 09:29:03 -05:00
Lisa Hsu
d939060ec6 Add Trap Level Zero to interrupts, remove some unreachable code that I forgot to remove last time.
--HG--
extra : convert_revision : 74c4c4591be5a66c21077a6fc5f3f60b0ee9bcc1
2007-01-11 09:18:31 -05:00
Ali Saidi
9d04510869 bug fixes to get us to 145m instructions
src/arch/sparc/intregfile.cc:
    some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
    fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
    legion always returns du and dl set, so we need to emulate that for now at least

--HG--
extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8
2007-01-10 22:19:13 -05:00
Ali Saidi
28a83c6d1c quiet/remove some warnings
fix implementation of cwp manipulation
implement PS0 and PS1 IMMU asis

src/arch/sparc/miscregfile.cc:
    get rid of some warnings
    fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are
src/arch/sparc/tlb.cc:
    implement PS0 and PS1 IMMU access ASIs
src/arch/sparc/ua2005.cc:
    make warning less verbose

--HG--
extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
2007-01-09 22:20:38 -05:00
Ali Saidi
7933aade85 add memory mapped disk device
configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
    add configuration for memory mapped disk
src/dev/sparc/SConscript:
    add memory mapped disk to sconscript

--HG--
extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
2007-01-09 22:16:49 -05:00
Lisa Hsu
0d7282d7ab pagetable.hh:
small fix so ALPHA_FS will build on macs
interrupts.hh:
small fix for alpha compile

src/arch/alpha/interrupts.hh:
    small fix for alpha compile
src/arch/alpha/pagetable.hh:
    small fix so ALPHA_FS will build on macs

--HG--
extra : convert_revision : 5fdbc68caa706d652b51807ac8f6bf58bcf72bdc
2007-01-08 20:50:45 -05:00
Lisa Hsu
032ea9b2db the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
src/arch/sparc/interrupts.hh:
    fill in how we do interrupts on sparc a little bit.

    1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
    2) fill in getInterrupts() a little bit.

    also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
    1) update formatting
    2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
    overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.

--HG--
extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
2007-01-08 18:18:28 -05:00
Lisa Hsu
b45219e7ae some formatting changes, and update how I do bitfields for HPSTATE and PSTATE to avoid name confusion.
src/arch/sparc/faults.cc:
    1) s/Resumeable/Resumable/gc
    2) s/if(/if (/gc
    3) keep variables lowercase
    4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv).
src/arch/sparc/faults.hh:
    s/Resumeable/Resumable/
src/arch/sparc/isa_traits.hh:
    This is unused and unnecessary.
src/arch/sparc/miscregfile.hh:
    add bitfield masks for some important ASRs (HPSTATE, PSTATE).

--HG--
extra : convert_revision : f0ffaf48de298758685266dfb90f43aff42e0a2c
2007-01-08 18:07:17 -05:00
Ali Saidi
a8b2d66661 change when legion-lock causes the simulation to die. It now happens after two consuctive differences since we compare stuff
at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early.

--HG--
extra : convert_revision : f237363eababb2aad67e5b41670cf40be048a042
2007-01-08 17:11:10 -05:00
Ali Saidi
2f4239a685 fix softint and partially implement hstick interrupts need to figure out how to do the acutal interrupting still
src/arch/sparc/miscregfile.cc:
    fix softint and fprs in miscregfile

--HG--
extra : convert_revision : cf98bd9c172e20f328f18e07dd05f63f37f14c87
2007-01-08 17:09:48 -05:00
Ali Saidi
4a8078192d set the softint appropriately on an timer compare interrupt
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly

src/arch/sparc/faults.cc:
    there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
    correct protection defines
src/arch/sparc/ua2005.cc:
    set the softint appropriately on an timer compare interrupt

--HG--
extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
2007-01-05 15:04:17 -05:00
Ali Saidi
b0f11f8f81 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : e8ac13e1222796ab362fabb9b19694682538da29
2007-01-04 20:22:56 -05:00
Ali Saidi
b46aa88435 Fix stick compare to work correctly and set checkInterrupts to true at the appropriate time
turn warnings into dprintfs

src/arch/sparc/miscregfile.cc:
    turn dprintfn into dprintfs

--HG--
extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
2007-01-04 20:22:45 -05:00
Nathan Binkert
e6b4fed75d set __name__ in the root m5 script to __m5_main__ so we can
tell if the script is run from m5 as the m5 script

--HG--
extra : convert_revision : 06f646cbb8c82444ef345115aa49324a4d3a2c9f
2007-01-03 10:16:22 -08:00
Nathan Binkert
e9a395c2ce Formatting
--HG--
extra : convert_revision : bf1eae73995f772a4343c8ebcb254818eeb5d949
2007-01-03 10:13:45 -08:00
Nathan Binkert
fc45d42d01 Add 'Time' as a parameter type that can accept various
formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit

--HG--
extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
2007-01-03 10:12:55 -08:00
Gabe Black
8840ebcb00 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
2007-01-03 00:52:30 -05:00
Kevin Lim
7d7f3d0e99 Fix up previous commit to proper logic.
src/cpu/o3/commit_impl.hh:
    Oops, changed the logic a little bit.  Fix it up to how it used to be.

--HG--
extra : convert_revision : df7f69b0997207b611374c3c92880f3a405e88be
2006-12-30 13:21:25 -05:00
Nathan Binkert
f6aa2ed47b Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/m5/incoming

--HG--
extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
2006-12-29 16:58:08 -08:00
Nathan Binkert
81e0ac3000 Formatting
--HG--
extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
2006-12-29 16:57:45 -08:00
Gabe Black
a0e8aa6737 Fixes to get non-delay slot ISAs (Alpha) working again, and pulling some debug output out of ifdefs.
--HG--
extra : convert_revision : 29d0969e2d3e809aac32262ba20907e6e4ef1a42
2006-12-28 14:35:31 -05:00
Gabe Black
3f2b25d997 Phased out DelaySlotInfo.
--HG--
extra : convert_revision : ab48db10caf38137300da63078aa9360f46b9631
2006-12-28 14:33:45 -05:00
Gabe Black
d24f60788f Some fixes for decode stage branches without delay slots. This will need some work to be compatible with delay slots too. Also changed some direct variable uses to use an accessor function.
--HG--
extra : convert_revision : b291292600e9d3e7e4a8255daf54342b736c7e35
2006-12-28 14:32:41 -05:00
Gabe Black
15df0a27bb Make sure the value of PC is actually updated now that the instruction target isn't set explicitly.
--HG--
extra : convert_revision : 4c00a219ac1d82abea78e4e8d70f529a435fdfe2
2006-12-28 14:29:17 -05:00
Gabe Black
b642ad00eb Implement a stub nnpc for alpha that is read only as npc+4.
--HG--
extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
2006-12-28 14:27:45 -05:00
Gabe Black
9ca6efdb60 Fixed NumMiscArchRegs. This is still a magic number, and it should be set automatically by the miscreg enum. I need to figure out how to do that without including the whole miscregfile.hh and making header spaghetti.
--HG--
extra : convert_revision : eb640c9ef10a188b96f6a079f91abc8f67b9d38c
2006-12-28 14:23:30 -05:00
Ali Saidi
b48a8fb347 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
2006-12-27 14:38:22 -05:00
Ali Saidi
ba14d6d0e1 Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48

src/arch/sparc/tlb.cc:
    Bug fixes in the TLB
    Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
    Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
    itb should be 64 entries too

--HG--
extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-27 14:38:07 -05:00
Ali Saidi
ff88f3b13a Compare legion and m5 tlbs for differences
Only print faults instructions that aren't traps or faulting loads

src/cpu/exetrace.cc:
    Compare the legion and m5 tlbs and printout any differences
    Only show differences if the instruction isn't a trap and isn't a memory
    operation that changes the trap level (a fault)
src/cpu/m5legion_interface.h:
    update the m5<->legion interface to add tlb data

--HG--
extra : convert_revision : 6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
2006-12-27 14:35:23 -05:00
Ali Saidi
b6dc902f6a Change MemoryAccess dprintfs to print the data as well
--HG--
extra : convert_revision : 51336fffa5e51a810ad2f6eb29b91c1bfd67824b
2006-12-27 14:32:26 -05:00
Nathan Binkert
9e90bfafb5 No need to use NULL, just use 0
The result of operator= cannot be an l-value

--HG--
extra : convert_revision : df97a57f466e3498bd5a29638cb9912c7f3e1bd4
2006-12-27 10:52:25 -08:00
Kevin Lim
0bd7518480 Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.
--HG--
extra : convert_revision : 5c334ec806305451b3883c7fd0ed9cd695c038bc
2006-12-26 01:43:18 -05:00
Nathan Binkert
2d029fe584 Make sure that all of the bits in the result are set
to some value.

--HG--
extra : convert_revision : 1f1700fd77531cbb8cfad7f04ce2b573fcdefdab
2006-12-24 15:15:12 -08:00
Nathan Binkert
e68a87e7fa remove some output formatting stuff that we don't use
--HG--
extra : convert_revision : 367917499d3d7aebd0a91dad28c915bc85def624
2006-12-24 14:06:56 -08:00
Nathan Binkert
139dcbe088 Fix copyright
--HG--
extra : convert_revision : 8ad7824885a5c4da80175c47ba5288aab55b06ca
2006-12-21 22:41:08 -08:00
Nathan Binkert
ecd1420341 Expose the C++ event queue to python via the python function
m5.internal.event.create().  It takes a python object and a
Tick and calls process() when the Tick occurs.

--HG--
extra : convert_revision : 5e4c9728982b206163ff51e6850a1497d85ad7a3
2006-12-21 22:38:50 -08:00
Nathan Binkert
ba191d85c2 style
--HG--
extra : convert_revision : 6bbaaa88a608081eebf706ff30293f38729415aa
2006-12-21 22:34:19 -08:00
Gabe Black
876c59fe8d Stub for SE mode gdb support for MIPS.
--HG--
extra : convert_revision : 2166b511c3615f7a2355f058a624e9ffe8259e65
2006-12-21 20:42:40 -05:00
Nathan Binkert
3f03e5f656 Create a wrapper function to more easily add swig stuff to the build
--HG--
extra : convert_revision : 3aaf540a9e314a88a8945579398f0d79aa85d5cf
2006-12-21 15:58:38 -08:00
Nathan Binkert
2cb2b50802 move the swig initialization calls from src/sim/main.cc to
src/python/swig/init.cc so that it's not as easy to forget
about it when you add a new swig module.

--HG--
extra : convert_revision : 5cc4ec0838e636aa761901effb8986de58d23e03
2006-12-21 15:49:16 -08:00
Nathan Binkert
9aecfb3e3b don't use (*activeThreads).begin(), use activeThreads->blah().
Also don't call (*activeThreads).end() over and over.  Just
call activeThreads->end() once and save the result.
Make sure we always check that there are elements in the list
before we grab the first one.

--HG--
extra : convert_revision : d769d8ed52da99532d57a9bbc93e92ddf22b7e58
2006-12-20 22:20:11 -08:00
Nathan Binkert
4b3538b609 Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/m5/incoming

--HG--
extra : convert_revision : c1724538f27091e16ca495c8fdf2df06f55f7668
2006-12-20 21:46:39 -08:00
Nathan Binkert
6487d358a4 <scold> Make sure that variables are always initalized! </scold>
--HG--
extra : convert_revision : 1e946d9b1e1def36f9b8a73986dabf1b77096327
2006-12-20 21:46:16 -08:00
Gabe Black
68a0e6f2e9 Fixes to get MIPS_SE to compile.
--HG--
extra : convert_revision : d173f212841341e436e9a38dcd3006d27886c1b8
2006-12-20 22:14:40 -05:00
Gabe Black
327f451eb7 Fixes to get ALPHA_FS and ALPHA_SE to compile again.
--HG--
extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
2006-12-20 20:44:06 -05:00
Gabe Black
f13155393d Initial work to make remote gdb available in SE mode. This is completely untested.
--HG--
extra : convert_revision : 3ad9a3368961d5e9e71f702da84ffe293fe8adc8
2006-12-20 18:39:40 -05:00
Gabe Black
841d76d37b Make sure the "stack_min" variable is page aligned.
--HG--
extra : convert_revision : e78c53778de83bdb2eca13d98d418b17b386ab29
2006-12-20 15:44:37 -05:00
Steve Reinhardt
6bc1e78d07 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 4bd4f8bb8e48e09562a2d9ae6eb7d061be973c5e
2006-12-19 02:11:48 -05:00
Ali Saidi
f27c686eb5 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : fa8ce7149973245a73bb562b9378db13be647a14
2006-12-19 02:11:47 -05:00
Ali Saidi
5e9d8795f2 fix twinx loads a little bit
bugfixes and demap implementation in tlb
ignore some more differencs for one cycle

src/arch/sparc/isa/formats/mem/blockmem.isa:
    twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
    fix the fault check for twinx
src/arch/sparc/tlb.cc:
    tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
    don't halt on a couple more instruction (ldx, stx) when things differ
    beacuse of the way tlb faults are handled in legion.

--HG--
extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71
2006-12-19 02:11:33 -05:00
Steve Reinhardt
9d7db8bb2b Streamline Cache/Tags interface: get rid of redundant functions,
don't regenerate address from block in cache so that tags can
turn around and use address to look up block again.

--HG--
extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
2006-12-18 23:07:52 -08:00
Steve Reinhardt
f655932700 No need to template prefetcher on cache TagStore type.
--HG--
rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc
extra : convert_revision : 56c0b51e424a3a6590332dba4866e69a1ad19598
2006-12-18 21:53:06 -08:00
Steve Reinhardt
1428b0de7d Get rid of generic CacheTags object (fold back into Cache).
--HG--
extra : convert_revision : 8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
2006-12-18 20:47:12 -08:00
Gabe Black
5b41ab694c Fix a place where the wrong width parameter was used, and set the nextNPC correctly on memory squashes.
--HG--
extra : convert_revision : 7914a48ea953607c48f93984e3b043098f0d7c62
2006-12-18 18:20:13 -05:00
Gabe Black
dfafe6741f Make sure you only handle branch delay slots specially when there actually was a branch.
--HG--
extra : convert_revision : ea6d33b1b9c2ba5c24225af4b10a9bd25558f1dd
2006-12-18 18:18:37 -05:00
Gabe Black
af1e8d2d40 Fixing the extended twin format to go with the new isa parser interface.
--HG--
extra : convert_revision : f41183cfa011b21e7ab8cbcdef0ac1d464692362
2006-12-18 18:17:30 -05:00
Nathan Binkert
0e78386874 Fix unittest compiles
--HG--
extra : convert_revision : 1163437081e1f1eab3f4512d04317dc94a673b9b
2006-12-18 14:08:42 -08:00
Nathan Binkert
9b40a13728 cast chars to int when we want to print integers so we get a number
instead of a character

--HG--
extra : convert_revision : 7bfa88ba23ad057b751eb01a80416d9f72cfe81a
2006-12-18 14:07:52 -08:00
Gabe Black
9e7dc34383 Merge zizzer.eecs.umich.edu:/.automount/zower/eecshome/m5/newmem
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/sparco3

--HG--
extra : convert_revision : f17800685609d8353ec14676f45fbb123fc4e6c3
2006-12-18 12:19:30 -05:00
Ali Saidi
6841f863c5 move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Make the TLB ok to translate QUAD_LDD

src/arch/sparc/isa/decoder.isa:
    move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
    Make QUAD_LDD asi ok to execute

--HG--
extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
2006-12-18 03:37:52 -05:00
Steve Reinhardt
d19d7aa8a5 Minor cleanup of new snippet/subst code.
--HG--
extra : convert_revision : d81e0d1356f3433e8467e407d66d4afb95614748
2006-12-17 23:09:36 -08:00
Steve Reinhardt
968048f56a Convert Alpha (and finish converting MIPS) to new
InstObjParam interface.

src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/fp.isa:
src/arch/alpha/isa/int.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/isa/mem.isa:
src/arch/alpha/isa/pal.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/util.isa:
    Get rid of CodeBlock calls to adapt to new InstObjParam interface.
src/arch/isa_parser.py:
    Check template code for operands (in addition to snippets).
src/cpu/o3/alpha/dyn_inst.hh:
    Add (read|write)MiscRegOperand calls to Alpha DynInst.

--HG--
extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
2006-12-17 19:27:50 -08:00
Gabe Black
c3ec52346b Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/operands.isa:
    Hand Merge

--HG--
extra : convert_revision : 4c54544e5c7a61f055ea9b00ccf5f8510df0e6c2
2006-12-17 11:55:24 -05:00
Gabe Black
81996f855a Compilation fixes.
--HG--
extra : convert_revision : 4932ab507580e0c9f7012398e71921ce58fc3c4e
2006-12-17 11:16:04 -05:00
Gabe Black
729dbb60e9 Added in the extended twin load format
src/arch/sparc/isa/decoder.isa:
    Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.

--HG--
extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
2006-12-17 11:15:37 -05:00
Gabe Black
c299c2562b Started removing "CodeBlock" objects from the mips isa description.
--HG--
extra : convert_revision : 2e174ecfce8c86732e1addfc23e961429b86a570
2006-12-17 10:54:17 -05:00
Gabe Black
220e99a29b Compilation fix after messy merge.
--HG--
extra : convert_revision : bf650dfe401377ce1b4c952aa8bfe3708c865472
2006-12-17 10:53:10 -05:00
Gabe Black
91b56d03fc Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/sparcfs

--HG--
extra : convert_revision : c8718b3df72b8c951c24742e8ce517a93bc23fe9
2006-12-16 12:55:55 -05:00
Gabe Black
c9f18981f9 Merge zizzer:/bk/sparcfs/
into  zower.eecs.umich.edu:/eecshome/m5/sparcfs

--HG--
extra : convert_revision : 2764b356ef01d1fcb6ed272e4ef96179cd651d4e
2006-12-16 12:55:15 -05:00
Gabe Black
b9d069167c Support for twin loads.
src/arch/sparc/isa/decoder.isa:
    Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
    Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
    Comment explaining twin load operands.

--HG--
extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
2006-12-16 12:54:28 -05:00
Gabe Black
fe73760388 Compiler error fix.
--HG--
extra : convert_revision : 39e2638a10bf3e821e8f3d4d8c664008c98fc921
2006-12-16 12:53:01 -05:00
Gabe Black
9d0ca61b7e Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
    Hand Merge

--HG--
extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
2006-12-16 11:35:40 -05:00
Gabe Black
f4f00c5ae9 Switch the endianness of data that's forwarded. This is the same sort of problem that was happening when stores went all the way to memory and back.
--HG--
extra : convert_revision : 09fece7ae934f542e51046d33505df3f7ec0b919
2006-12-16 09:35:09 -05:00
Gabe Black
96e5086c81 Make fetch detect when a branch is happening, rather than trying to compute when.
--HG--
extra : convert_revision : 1a8edc004570abb48e6c4cdf1b43c5699866838e
2006-12-16 09:34:20 -05:00
Gabe Black
a6eb16adb4 Accidently "cleaned" away the NPC parameter to the constructor.
--HG--
extra : convert_revision : 46670ee86000dfb171d327eb8f58555a4afb2360
2006-12-16 07:47:33 -05:00
Gabe Black
f410d5f4e0 Don't have "predict" set the predicted target of the instruction. Do that explicitly when you use predict.
--HG--
extra : convert_revision : 8b613bb365b31ffaef1cea9fd789abe46219bdcf
2006-12-16 07:39:44 -05:00
Gabe Black
569e0e883b Add in constants which let you explicitly check if endian conversion would do anything. This was needed for a case where a piece of data was within a larger data type. When the larger data type was swapped, the location of the smaller data type would move.
--HG--
extra : convert_revision : 4c904c964678529c72b8f1044dfcb400604f6654
2006-12-16 07:37:33 -05:00
Gabe Black
c6944e320c Add in capability to return to unblocking after a squash. This is needed because if you don't squash -all- the instructions, you need to keep clearing out whatever is left in the skid buffer.
--HG--
extra : convert_revision : 7308eda27f4366348cf5fce71ddfa4b217bc172d
2006-12-16 07:35:56 -05:00
Gabe Black
244506ae12 Make sure endian conversion is done on the memory data when it's just set to an existing buffer.
--HG--
extra : convert_revision : 5a890091b6a31b5414acbf68f19e28d7122a98d7
2006-12-16 07:34:34 -05:00
Gabe Black
6413b74e4f Make the decoder use the new setup in the dyninsts for branch prediction.
--HG--
extra : convert_revision : 9a6d6c93e5b40a55774891df54d290ff557b322c
2006-12-16 07:33:08 -05:00
Gabe Black
37b9966eb4 Made branch delay slots get squashed, and passed back an NPC and NNPC to start fetching from.
--HG--
extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
2006-12-16 07:32:06 -05:00
Gabe Black
4d66ddbe35 Added a predicted NPC field, explicitly stored whether the instruction was predicted taken or not.
--HG--
extra : convert_revision : ba668af302ca4d8a3a032e907d5058e1477f462a
2006-12-16 07:22:19 -05:00
Gabe Black
181f4f32f6 Made changes to CWP be non speculative.
--HG--
extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
2006-12-16 07:10:58 -05:00
Gabe Black
6aa06a26b7 Changes to the isa_parser and affected files to fix an indexing problem with split execute instructions and miscregs aliasing with integer registers.
src/arch/isa_parser.py:
    Rearranged things so that classes with more than one execute function treat operands properly.
    1. Eliminated the CodeBlock class
    2. Created a SubOperandList
    3. Redefined how InstObjParams is constructed

    To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.

    Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
    Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
    Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
    Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.

--HG--
extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
2006-12-16 07:10:04 -05:00
Lisa Hsu
4da37bcd1b Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : a6a40a3bc2e07bc7828de08fa2ce1c847105483d
2006-12-15 18:07:39 -05:00
Lisa Hsu
385a3ff054 small change to eliminate address range overlap.
--HG--
extra : convert_revision : c8309a8774265a707c87c4f516bec1f81aff4a79
2006-12-15 17:58:20 -05:00
Lisa Hsu
551ba56ae2 little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.

src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
    Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
    pioSize indicates SIZE, not a mask

--HG--
extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948
2006-12-15 17:55:47 -05:00
Lisa Hsu
991146218d Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
2006-12-15 13:27:53 -05:00