to be consistent with the way that the stl works. It also makes
lots of other stuff easier. (Maybe those guys were smart?)
Overload the various comparison operators so that you can test
for overlapping of ranges, etc.
base/range.hh:
Totally rework the Range class. Now the range is from [start, end)
to be consistent with the way that the stl works. It also makes
lots of other stuff easier. (Maybe those guys were smart?)
Overload the various comparison operators so that you can test
for overlapping of ranges, etc.
make parse function private and offer operator= instead
isValid -> valid
and for you erik, I add comments
test/Makefile:
add range.o
test/rangetest.cc:
better tests
--HG--
extra : convert_revision : dd58720aa3d02f20b03e933f2eaa3320c82bb27a
benchmarks for alpha-linux.
arch/alpha/alpha_linux_process.cc:
Added some more ioctl commands to ignore.
Set unlink and rename to the new functions.
Ignore setrlimit, times and rt_sigaction.
Should eventually provide a function for times.
arch/alpha/alpha_tru64_process.cc:
Added some more ioctl commands to ignore.
Set unlink and rename to the new functions.
Ignore setrlimit.
sim/syscall_emul.cc:
Added implementations for unlink and rename.
sim/syscall_emul.hh:
Added unlink and rename functions.
Added a couple more ioctl requests to ignore.
Print out the PC of any ioctl commands that fail.
--HG--
extra : convert_revision : 8af21c7fa7d0645d3f9324c9ce70ad33590c3c8e
execution pipeline (Alpha trapb & excb).
Add support for write memory barriers (mostly impacts
store buffer).
Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.
arch/alpha/isa_desc:
Implement trapb, excb, mb, and wmb as insts with
no execution effect (empty execute() function) but
with flags that indicate their side effects.
Also make sure every instruction that needs to go to
the execute stage has a real opClass value, since we
are now using No_OpClass to signal insts that can get
dropped at dispatch.
StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
Add flags to indicate serializing insts (trapb, excb) and
memory and write barriers.
Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
Make name() return value const.
--HG--
extra : convert_revision : 39520e71469fa20e0a7446b2e06b494eec17a02c
The last change only caught the ones with types that
started with capitals. This pass catches the rest
(mostly STL and uint*_t types).
base/cprintf_formats.hh:
cpu/simple_cpu/simple_cpu.cc:
sim/serialize.cc:
sim/serialize.hh:
Change "foo_t& foo" to "foo_t &foo".
--HG--
extra : convert_revision : fc7f7425db2aef33e490f952b5ce74c8c36d0d41
base/kgdb.h:
Remove flags that aren't used
base/remote_gdb.cc:
Better debugging:
- Give each class a name() function so that the trace infrastructure
knows the correct object name.
- Make the remote debugger capable of detach.
- Split out the RGDB trace flag into a bunch of specific flags.
Remove dead code
Add a new trap type
base/remote_gdb.hh:
Add a name() to the various objects for the trace system
base/trace.hh:
don't need a using directive
add DPRINTFNR: debug printf, no flag, raw output
kern/tru64/tru64_system.cc:
use the INT trap type instead of IF
--HG--
extra : convert_revision : 25e610216c6f43d5d328651bba915f71bade059e
arch/alpha/isa_desc:
Add missing branchTarget() method for indirect branches.
cpu/static_inst.hh:
Add comment clarifying when branchTarget() can be used
on indirect branches.
--HG--
extra : convert_revision : 0dcfb36a9792a338cefceb3d1501825abace7ac5
the ROB (so we know they're correct-path) before we mark them ready to issue.
--HG--
extra : convert_revision : be1d431bdc939100d79a5fea3e415b3acf9e8d75
This primarily to be internally consistent (sometimes we used one,
sometimes the other, even within the same line of code!).
I picked the latter to be symmetric with "Foo *foo".
base/cprintf_formats.hh:
base/range.hh:
base/refcnt.hh:
base/res_list.hh:
base/statistics.hh:
base/str.hh:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/syscall_emul.hh:
Change "Foo& foo" declarations to "Foo &foo".
--HG--
extra : convert_revision : ca1b0e85a578b539214bda3b8d61ac23792f2e87
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
Change MemReqPtr parameters to references.
--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
setup-spec script
util/setup-spec:
Made some changes so the information contained in the ini file explains
what the init_param value corresponds to
--HG--
extra : convert_revision : 4082209f920244c262150c224a92ea21a55febd5
not while printing out the data. This allows the data
to be dumped more than once.
base/cprintf.hh:
need a destructor
--HG--
extra : convert_revision : 235e9fe24488ac4c0ae1b562ef9fa6e0bd1e899c
special console values separately.
dev/alpha_console.cc:
use new console specific input function
--HG--
extra : convert_revision : 08997d6115d2aac3a26cac2774b3c3fc0cd76ab0
statStream catchall that we had before)
Also provide an optional output directory that multiple simulator output
files can be written to.
Make most output files use the output directory
base/misc.cc:
send warnings to the outputStream as well
base/trace.cc:
dprintf_stream defaults to cerr
dev/console.cc:
use the output directory for the console output if it exists
dev/etherdump.cc:
dump to the output directory if it exists
sim/builder.cc:
sim/builder.hh:
move constructor and destructor to .cc file
use a function to get the stream that the builder dumps its
output to, and create a separate file in the output directory
if able
sim/main.cc:
statStream -> outputStream
sim/serialize.cc:
dump checkpoints to the output directory if specified
sim/universe.cc:
provide an output stream for simulator output. (This takes place of the
statStream catchall that we had before)
Also provide an optional output directory that multiple simulator output
files can be written to.
--HG--
extra : convert_revision : 03abce20edbbf7ec19c9ddd8d69ec8485c383532
arch/alpha/isa_desc:
don't say warn: Warning:
base/misc.cc:
avoid printing two newlines in a row
sim/main.cc:
print out a message just before we enter the event queue
--HG--
extra : convert_revision : 2a824d4b67661903fc739a0fb0759aa91d72382c
