Commit graph

10 commits

Author SHA1 Message Date
Gabe Black 118b9dc1f9 Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however.
--HG--
extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
2006-11-03 04:25:33 -05:00
Gabe Black c8fc116c76 Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the
--HG--
extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
2006-11-03 02:25:39 -05:00
Gabe Black b565660c42 Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
2006-11-01 19:00:59 -05:00
Gabe Black 2b11b47357 Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-11-01 16:44:45 -05:00
Kevin Lim bfd5eb2b08 Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    No need for mem parameter any more.
src/cpu/checker/cpu.cc:
    Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
    Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
    Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
    Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
    Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
    Remove memory parameter.

--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
2006-10-31 14:33:56 -05:00
Gabe Black 038217049a Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
--HG--
extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
2006-10-31 03:37:01 -05:00
Gabe Black 74e80fc6c7 Some touchup to the reorganized includes and "using" directives.
--HG--
extra : convert_revision : 956c80d6d826b08e52c0892a480a0a9b74b96b9d
2006-08-15 05:49:52 -04:00
Gabe Black 74546aac01 Cleaned up include files and got rid of many using directives in header files.
--HG--
extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
2006-08-15 05:07:15 -04:00
Korey Sewell 51261196bd now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
src/cpu/o3/alpha/cpu.cc:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/impl.hh:
    filenames
src/cpu/o3/alpha/thread_context.hh:
    public
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use O3CPUImpl ... not Alpha
src/cpu/o3/checker_builder.cc:
    filename

--HG--
extra : convert_revision : 6eb739909699ade1e2a9d63637b182413ceebc69
2006-06-30 20:49:31 -04:00
Korey Sewell d9ef772e8d Make O3CPU model independent of the ISA
Use O3CPU when building instead of AlphaO3CPU.

I could use some better python magic in the cpu_models.py file!

AUTHORS:
    add middle initial
SConstruct:
    change from AlphaO3CPU to O3CPU
src/cpu/SConscript:
    edits to build O3CPU instead of AlphaO3CPU
src/cpu/cpu_models.py:
    change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model...

    Actually, some Python expertise could be used here. The 'env' variable is not
    passed to this file, so I had to parse through the ARGV to find the ISA...
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use isa_specific.hh
src/sim/process.cc:
    only initi NextNPC if not ALPHA
src/cpu/o3/alpha/cpu.cc:
    alphao3cpu impl
src/cpu/o3/alpha/cpu.hh:
    move AlphaTC to it's own file
src/cpu/o3/alpha/cpu_impl.hh:
    Move AlphaTC to it's own file ...
src/cpu/o3/alpha/dyn_inst.cc:
src/cpu/o3/alpha/dyn_inst.hh:
src/cpu/o3/alpha/dyn_inst_impl.hh:
    include paths
src/cpu/o3/alpha/impl.hh:
    include paths, set default MaxThreads to 2 instead of 4
src/cpu/o3/alpha/params.hh:
    set Alpha Specific Params here
src/python/m5/objects/O3CPU.py:
    add O3CPU class
src/cpu/o3/SConscript:
    include isa-specific build files
src/cpu/o3/alpha/thread_context.cc:
    NEW HOME of AlphaTC
src/cpu/o3/alpha/thread_context.hh:
    new home of AlphaTC
src/cpu/o3/isa_specific.hh:
    includes ISA specific files
src/cpu/o3/params.hh:
    base o3 params
src/cpu/o3/thread_context.hh:
    base o3 thread context
src/cpu/o3/thread_context_impl.hh:
    base o3 thead context impl

--HG--
rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc
rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh
rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc
rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh
rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh
rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e
2006-06-30 19:52:08 -04:00
Renamed from src/cpu/o3/alpha_cpu_impl.hh (Browse further)